FIN3385MTDX Fairchild Semiconductor, FIN3385MTDX Datasheet
FIN3385MTDX
Specifications of FIN3385MTDX
FIN3385MTDXTR
Related parts for FIN3385MTDX
FIN3385MTDX Summary of contents
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... Compatible with TIA/EIA-644 Specification 56-Lead TSSOP Package Ordering Information Operating Part Number Temperature Range FIN3383MTDX FIN3384MTDX -10 to +70°C FIN3385MTDX FIN3386MTDX For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Table 1. Display Panel Link Serializer / Deserializer Chip Matrix CLK Part Frequency FIN3385 85 FIN3383 ...
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... Block Diagrams Figure 1. FIN3385 and FIN3383 Transmitter Functional Diagram Figure 2. FIN3386 and FIN3384 Receiver Functional Diagram © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 2 www.fairchildsemi.com ...
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... I PLL PLL GND I LVDS LVDS GND GND I © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 Truth Table TxIn Active Active Floating Floating Don’t Care Notes: 1. The outputs of the transmitter or receiver remains in a high-impedance state until V reaches 2V. 2. TxCLKOut± settles at a free-running frequency ...
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... PLL GND I LVDS LVDS GND GND I © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 Number of Pins 4/3 Negative LVDS Differential Data Output 4/3 Positive LVDS Differential Data Output 1 Negative LVDS Differential Data Input 1 Positive LVDS Differential Clock Input 28/21 LVTTL Level Data Output, goes HIGH for /PwrDn LOW ...
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... Shorted means (± inputs are shorted to each other, or ± inputs are shorted to each other and ground or V either ± inputs are shorted to ground or V still in the valid range (greater than 100mV) and V recognized and the part responds normally. © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 PwrDn Normal < ...
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... V Maximum Supply Noise Voltage CCNPP Note: 8. 100mV V noise should be tested for frequency at least up to 2MHz. All the specifications should be met CC under such a noise. © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 Parameter I/O to GND All Pins Parameter (8) 6 Min. Max. ...
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... The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 =3.3V; minimum and maximum are at over supply voltages and operating ...
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... Transmitter Output Pulse Position of Bit 4 TPPB4 t Transmitter Output Pulse Position of Bit 5 TPPB5 t Transmitter Output Pulse Position of Bit 6 TPPB6 © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 =3.3V; minimum and maximum are at over supply voltages and operating CC Parameter Conditions Figure 9 (10% to 90%) ...
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... Figure 18). Figure 20 shows the skew between the first data bit and clock output. A two-bit cycle delay is guaranteed when the MSB is output from transmitter. 14. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter of less than 2ns. © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 (13) -0.2 a-0 ...
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... Pattern with Load I CCWR 3:21 Receiver Power Supply Current for Worst Case (15) Pattern with Load Powered-Down Supply I CCPDT Current © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 =3.3V. Minimum and maximum values are over supply voltage and CC Conditions I =-0.4mA OH I =2mA OL ...
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... Total channel latency from serializer to deserializer 17. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position. © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 (Continued) =3.3V; minimum and maximum are at over supply voltages and operating ...
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... Total channel latency from serializer to deserializer 20. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum / maximum bit position. © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 Conditions Figure 12 ...
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... Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages ( 1.25 1.15 2.40 2.30 0.10 0 1.50 0.90 2.40 1.80 0.60 0 © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 Resulting Differential Input Voltage (mV 1.15 100 1.25 -100 2.30 100 2.40 -100 ...
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... Figure 8. Transmitter LVDS Output Load and Transition Times Figure 9. Transmitter Setup/Hold and HIGH/LOW Times (Rising-Edge Strobe) Figure 10. Transmitter Input Clock Transition Time Figure 11. Transmitter Outputs Channel-to-Channel Skew © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 Figure 7. Worst-Case Test Pattern 14 www.fairchildsemi.com ...
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... RHRC Figure 13. Transmitter Clock-In to Clock-Out Delay (Rising-Edge Strobe) Figure 14. Receiver Clock-In to Clock-Out Delay (Falling-Edge Strobe) © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 (Continued) Figure 15. Receiver Phase Lock Loop Set Time 15 www ...
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... Note: 24. This output date pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit mapping difference. Two-bit cycle delay is guaranteed with the MSB is output from transmitter. © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 (Continued) Figure 16. Transmitter Power-down Delay Figure 17 ...
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... RSKM The minimum and maximum pulse position values are based on the bit position of each of the seven bits within the LVDS data stream across PVT (Process, Voltage Supply, and Temperature). © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 (Continued) Figure 20. Transmitter Output Pulse Bit Position Figure 21 ...
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... The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst-case of clock-edge jump (3ns) from graphical controllers. Cycle-to- cycle jitter at TxCLKOut pin should be measured cross V <2MHz). © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 (Continued) range with 100mV noise (V ...
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... Note: 30. The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. © 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 (Continued) Figure 25. “16 Grey-Scale” Test Pattern Figure 26 ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 • Rev. 1.0.4 21 www.fairchildsemi.com ...