QLX4600LIQT7 Intersil, QLX4600LIQT7 Datasheet - Page 10

• Manufacturer Part Number: QLX4600LIQT7
• Description: IC EQUALIZER REC 6.25GBPS 46QFN
• Manufacturer: Intersil
• Series: QLx™r

Specifications of QLX4600LIQT7

• Applications: Data Transport
• Voltage - Supply: 1.1 V ~ 1.3 V
• Package / Case: 46-WQFN
• Mounting Type: Surface Mount
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Other names: QLX4600LIQT7-TR

QLx4600-SL30 v3.0
In4[P,N]
LOS1
LOS2
GND
DI
DO
CP3[A,B,C]
CP4[A,B,C]
MODE
LOS4
LOS3
Out4[N,P]
Out3[N,P]
Out2[N,P]
Out1[N,P]
BGREF
CP2[C,B,A]
CP1[C,B,A]
ENB
CLK
Exposed Pad
Pin Name
11, 12
13
14
15
16
17
18, 19, 20
21, 22, 23
24
25
26
27, 28
30, 31
33, 34
36, 37
38
39, 40, 41
42, 43, 44
45
46
-
Pin Number
Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz
frequency response is recommended.
ground
Serial data input, CMOS logic. Input for serial data stream to program internal registers controlling the boost for
all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides the boost setting established on CP
control pins. Internally pulled down.
Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four equalizers.
Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed by 21 clock cycles.
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the boost
level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the boost
level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Boost-level control mode input, CMOS logic. Allows serial programming of internal registers through pins DI,
ENB, and Clk when set HIGH. Resets all internal registers to zero and uses boost levels set by CP pins when
set LOW. If serial programming is not used, this pin should be grounded.
Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz
frequency response is recommended.
Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz
frequency response is recommended.
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz
frequency response is recommended.
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz
frequency response is recommended.
External bandgap reference resistor. Recommended value of 6.04kΩ ±1%.
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the boost
level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the boost
level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and CLK pins only
when the ENB pin is ‘LOW’. Internally pulled down.
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI is latched on
the rising clock edge. Clock speed is recommended to be between 10MHz and 20MHz. Internally pulled down.
Exposed ground pad. For proper electrical and thermal performance, this pad should be connected to the PCB
ground plane.
LOS indicator 1. High output when equalized In1 signal is below DT threshold.
LOS indicator 2. High output when equalized In2 signal is below DT threshold.
LOS indicator 4. High output when equalized In4 signal is below DT threshold.
LOS indicator 3. High output when equalized In3 signal is below DT threshold.
TABLE 5: PIN DESCRIPTIONS
10
Description
QLx4600-SL30
©2009 Quellan, Inc