PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 32

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.7.6
4.7.7
Pericom Semiconductor
Table 4-5 (assuming no disconnect is received from the target).
DELAYED READ COMPLETION ON INITIATOR BUS
When the transaction has been completed on the target bus, and the delayed read data is
at the head of the read data queue, and all ordering constraints with posted write
transactions have been satisfied, the PI7C7300D transfers the data to the initiator when
the initiator repeats the transaction. For memory read transactions, PI7C7300D aliases
the memory read, memory read line, and memory read multiple bus commands when
matching the bus command of the transaction to the bus command in the delayed
transaction queue. PI7C7300D returns a target disconnect along with the transfer of the
last DWORD of read data to the initiator. If PI7C7300D initiator terminates the
transaction before all read data has been transferred, the remaining read data left in data
buffers is discarded.
When the master repeats the transaction and starts transferring prefetchable read data
from data buffers while the read transaction on the target bus is still in progress and
before a read boundary is reached on the target bus, the read transaction starts operating
in flow-through mode. Because data is flowing through the data buffers from the target to
the initiator, long read bursts can then be sustained. In this case, the read transaction is
allowed to continue until the initiator terminates the trans-action, or until an aligned 4KB
address boundary is reached, or until the buffer fills, whichever comes first. When the
buffer empties, PI7C7300D reflects the stalled condition to the initiator by disconnecting
the initiator with data. The initiator may retry the transaction later if data are needed. If
the initiator does not need any more data, the initiator will not continue the disconnected
transaction. In this case, PI7C7300D will start the master timeout timer. The remaining
read data will be discarded after the master timeout timer expires. To provide better
latency, if there are any other pending data for other transactions in the RDB (Read Data
Buffer), the remaining read data will be discarded even though the master timeout timer
has not expired.
PI7C7300D implements a master timeout timer that starts counting when the delayed
read completion is at the head of the delayed transaction queue, and the read data is at the
head of the read data queue. The initial value of this timer is program-mable through
configuration register. If the initiator does not repeat the read transaction and before the
master timeout timer expires (2
read data from its queues. PI7C7300D also conditionally asserts P_SERR# (see Section
7.4).
PI7C7300D has the capability to post multiple delayed read requests, up to a maximum
of four in each direction. If an initiator starts a read transaction that matches the address
and read command of a read transaction that is already queued, the current read
command is not posted as it is already contained in the delayed transaction queue.
See Section 6 for a discussion of how delayed read transactions are ordered when
crossing PI7C7300D.
FAST BACK-TO-BACK READ TRANSACTION
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default), PI7C7300D discards the read transaction and
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D