PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 58

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3
Pericom Semiconductor
Table 7-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT
Table 7-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C7300D to data parity errors are presented
according to the type of transaction in progress. This section organizes the responses of
PI7C7300D to data parity errors according to the status bits that PI7C7300D sets and the
signals that it asserts.
Table 7-1 shows setting the detected parity error bit in the status register, corresponding
to the primary interface. This bit is set when PI7C7300D detects a parity error on the
primary interface.
X = don’t care
Table 7-2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C7300D detects a
parity error on the secondary interface.
X = don’t care
Primary Detected
Parity Error Bit
0
0
1
0
1
0
0
0
1
0
0
0
Secondary
Detected Parity
Error Bit
0
1
0
0
0
0
0
1
0
0
0
1
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Page 58 of 107
Direction
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
3-PORT PCI-TO-PCI BRIDGE
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
November 2005 - Revision 1.01
Primary/
Secondary Parity
Error Response
Bits
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
Primary/
Secondary Parity
Error Response
Bits
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
PI7C7300D