PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 81

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.17
14.1.18
Pericom Semiconductor
MEMORY BASE REGISTER – OFFSET 20h
MEMORY LIMIT REGISTER – OFFSET 20h
Bit
27
28
29
30
31
Bit
3:0
15:4
Bit
19:16
31:20
Function
Signaled Target
Abort
Received Target
Abort
Received Master
Abort
Received System
Error
Detected Parity
Error
Function
Memory Base
Address [15:4]
Function
Memory Limit
Address [31:20]
Type
R/WC
R/WC
R/WC
R/WC
R/WC
Type
R/O
R/W
Type
R/O
R/W
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Description
Set to 1 (by a target device) whenever a target abort cycle occurs on
its secondary (S1 or S2) interface
Reset to 0
Set to 1 (by a master device) whenever transactions on its secondary
(S1 or S2) interface are terminated with target abort
Reset to 0
Set to 1 (by a master) when transactions on its secondary (S1 or S2)
interface are terminated with Master Abort
Reset to 0
Set to 1 when S1_SERR# or S2_SERR# is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the
secondary (S1 or S2) interface
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be 0.
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be FFFFFh.
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D