PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 63

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4
8
Pericom Semiconductor
SYSTEM ERROR (SERR#) REPORTING
PI7C7300D uses the P_SERR# signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section
7.2.3.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the
following conditions apply:
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7300D
asserts P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and
the SERR# forward enable bit is set in the bridge control register. In addition,
PI7C7300D also sets the received system error bit in the secondary status register.
PI7C7300D also conditionally asserts P_SERR# for any of the following reasons:
The device-specific P_SERR# status register reports the reason for the assertion of
P_SERR#. Most of these events have additional device-specific disable bits in the
P_SERR# event disable register that make it possible to mask out P_SERR# assertion for
specific events. The master timeout condition has a SERR# enable bit for that event in
the bridge control register and therefore does not have a device-specific disable bit.
EXCLUSIVE ACCESS
This chapter describes the use of the LOCK# signal to implement exclusive access to a
target for transactions that cross PI7C7300D.
For PI7C7300D to assert P_SERR# for any reason, the SERR# enable bit must be
set in the command register.
Whenever PI7C7300D asserts P_SERR#, PI7C7300D must also set the signaled
system error bit in the status register.
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
received)
Parity error reported on target bus during posted write transaction (see previous
section)
Delayed write data discarded after 2
received)
Delayed read data cannot be transferred from target after 2
target retries received)
Master timeout on delayed transaction
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(default) attempts to deliver (2
(default) attempts to deliver (2
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
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(default) attempts (2
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target retries
target retries
PI7C7300D
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