NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 16

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1 2
MDC
MDIO
TXCLK
TXD3
TXD2
TXD1
TXD0
TXER
TXEN
COL
CRS
RXCLK
RXD3
RXD2
RXD1
RXD0
RXER
RXDV
E t h e r n e t i n t e r f a c e M A C
Mnemonic
MII management clock
Management data IO
Transmit clock
Transmit data signals
Transmit coding error
Transmit enable
Transmit collision
Receive carrier sense
Receive clock
Receive data signals
Receive error
Receive data valid
Signal
N S 7 5 2 0 D a t a s h e e t
Provides the clock for the MDIO serial data channel. The MDC signal
is an NS7520 output. The frequency is derived from the system
operating frequency per the CLKS field setting (see the CLKS field in
Table 69: "MII Management Configuration register bit definition" on
page 191).
A bi-directional signal that provides a serial data channel between the
NS7520 and the external Ethernet PHY module.
An input to the NS7520 from the external PHY module. TXCLK
provides the synchronous data clock for transmit data.
Nibble bus used by the NS7520 to drive data to the external Ethernet
PHY. All transmit data signals are synchronized to TXCLK.
In ENDEC mode, only TXD0 is used for transmit data.
Output asserted by the NS7520 when an error has occurred in the
transmit data stream.
Asserted when the NS7520 drives valid data on the TXD outputs.
This signal is synchronized to TXCLK.
Input signal asserted by the external Ethernet PHY when a collision
is detected.
Asserted by the external Ethernet PHY whenever the receive medium
is non-idle.
An input to the NS7520 from the external PHY module. The receive
clock provides the synchronous data clock for receive data.
Nibble bus used by the NS7520 to input receive data from the
external Ethernet PHY. All receive data signals are synchronized to
RXCLK.
In ENDEC mode, only RXD0 is used for receive data.
Input asserted by the external Ethernet PHY when the Ethernet PHY
encounters invalid symbols from the network.
Input asserted by the external Ethernet PHY when the PHY drives
valid data on the RXD inputs.
Description
0 3 / 2 0 0 6