NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 20

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System mode (test support)
PLLTST_, BISTEN_, and SCANEN_ primary inputs control different test modes for both functional
and manufacturing test operations (see Table 3: "NS7520 test modes" on page 22).
JTAG test
JTAG boundary scan allows a tester to check the soldering of all signal pins and tri-state all
outputs.
ARM debugger signal descriptions
1 6
PLLTST_
BISTEN_
SCANEN_
TDI
TDO
TMS
TRST_
TCK
TDI
TDO
TMS
S y s t e m m o d e ( t e s t s u p p o r t )
Symbol
Symbol
Mnemonic
Test data in
Test data out
Test mode select
Signal
N15
M15
L13
N14 U
M13
M12 U
M14
P15
Pin
Pin
N S 7 5 2 0 D a t a s h e e t
I
I
I
I
O
I
I
I
I/O
I/O
TDI operates the JTAG standard. Consult the JTAG specifications
for use in boundary-scan testing. These signals meet the
requirements of the Raven and Jeeni debuggers.
TDO operates the JTAG standard. Consult the JTAG specifications
for use in boundary-scan testing. These signals meet the
requirements of the Raven and Jeeni debuggers.
TMS operates the JTAG standard. Consult the JTAG specifications
for use in boundary-scan testing. These signals meet the
requirements of the Raven and Jeeni debuggers.
Description
2
OD
OD
Encoded with BISTEN_ and SCANEN_
Add an external pullup to 3.3V or pulldown to GND.
Encoded with PLLTST_ and SCANEN_
Add an external pullup to 3.3V or pulldown to GND.
Encoded with BISTEN_ and PLLTST_
Add an external pullup to 3.3V or pulldown to GND.
Test data in.
Test data out.
Test mode select.
Test mode reset.
Requires external termination when not being used (see
Figure 3, "TRST_ termination," on page 17 for an
illustration of the termination circuit on the development
PCB).
Test mode clock.
Add an external pullup to 3.3V.
Description
Description
0 3 / 2 0 0 6