NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 7

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The NS7520 is available in grades operating at three maximum operating frequencies: 36 MHz,
46 MHz, and 55 MHz. The operating frequency is set during bootstrap initialization, using pins
A[8:0]. These address pins load the PLL Settings register on powerup reset. A[8:7] determines IS
(charge pump current); A[6:5] determines FS (output divider), and A[4:0] defines ND (PLL
multiplier). Each bit in A[8:0] can be set individually. See the discussion of the PLL Settings register
in the NS7520 Hardware Reference for more information.
Operating frequency
Serial ports
Power and Operating Voltages
extractions
synchronous operation
switching)
switching)
switching)
Two fully independent serial ports (UART, SPI)
Digital phase lock loop (DPLL) for receive clock
32-byte transmit/receive FIFOs
Internal programmable bit-rate generators
Bit rates 75–230400 in 16X mode
Bit rates 1200 bps–4 Mbps in 1X mode
Flexible baud rate generator, external clock for
Receive-side character and buffer gap timers
Four receive-side data match detectors
500 mW maximum at 55 MHz (all outputs
418 mW maximum at 46 MHz (all outputs
291 mW maximum at 36 MHz (all outputs
3.3 V — I/O
1.5 V — Core
Bus interface
with 256 Mb addressing per chip select
SDRAM, Flash, and EEPROM without external
glue
multiplexer and programmable refresh frequency
modes (see "NS7520 bootstrap initialization" on
page 22)
Five independent programmable chip selects
Chip select support for SRAM, FP/EDO DRAM,
8-, 16-, and 32-bit peripheral support
External address decoding and cycle termination
Dynamic bus sizing
Internal DRAM/SDRAM controller with address
Internal refresh controller (CAS before RAS)
Burst-mode support
0–63 wait states per chip select
Address pins that configurem chip operating
w w w . d i g i . c o m
O p e r a t i n g f r e q u e n c y
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