NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet
NS7520B-1-C36
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NS7520B-1-C36 Summary of contents
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Part number/version: 90000353_G Release date: September 2007 www.digiembedded.com NS7520 Hardware Reference ...
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... Printed in the United States of America. All rights reserved. Digi, Digi International, the Digi logo, NetSilicon, a Digi International Company, NET+, NET+OS and NET+Works are trademarks or registered trademarks of Digi International, Inc. in the United States and other countries worldwide. All other trademarks are the property of their respective owners. ...
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Using This Guide Using This Guide This guide provides information about the NS7520 32-bit networked microprocessor. The NS7520 is part of the NET+ARM line of SoC (System-on- Chip) products, and supports high-bandwidth applications for intelligent networked devices. The NET+ARM family ...
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Digi information Related documentation For additional documentation, see the Documentation folder in the NET+OS Start menu. Documentation updates Digi occasionally provides documentation updates on the Web site (www.digiembedded.com/support). Be aware that if you see differences between the documentation you received ...
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Contents NS7520 Features ......................................................................... 2 Key features and operating modes of the major NS7520 modules ........ 2 ...
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Exception vector table.......................................................... 33 Detail of ARM exceptions ....................................................... 34 Entering and exiting an exception (software action) ...................... 37 Hardware Interrupts.................................................................... 39 FIRQ and IRQ lines ............................................................... 39 Interrupt controller.............................................................. 39 Interrupt sources................................................................. ...
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System Control register ......................................................... 63 System Status register .......................................................... 68 Software Service register....................................................... 69 Timer Control registers ......................................................... 70 Timer Status registers........................................................... 73 PORTA Configuration register.................................................. 73 PORTC Configuration register.................................................. 77 Interrupts ................................................................................ 80 Interrupt controller registers .................................................. 81 C ...
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SDRAM read cycles..............................................................120 SDRAM write cycles .............................................................122 Peripheral page burst size ...........................................................124 DMA module ............................................................................128 Fly-by operation transfers.....................................................128 Memory-to-memory operation ................................................129 DMA ...
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Ethernet General Status register (EGSR) bit definitions ..................164 Ethernet FIFO Data register ...................................................167 Ethernet Transmit Status register............................................168 Ethernet Receive Status register .............................................173 MAC Configuration Register 1 .................................................176 MAC Configuration Register 2 .................................................178 Back-to-Back Inter-Packet-Gap register.....................................182 Non-Back-to-Back Inter-Packet-Gap register ...............................183 Collision ...
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Serial Channel 1, 2 Bit-Rate registers .......................................241 Serial Channel 1, 2 FIFO registers ............................................250 Serial Channel 1, 2 Receive Buffer Gap Timer .............................250 Serial Channel 1, 2 Receive Character Gap Timer.........................252 Serial Channel 1,2 Receive Match register..................................254 Serial Channel 1, ...
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Error in “No Connect” pin terminations.....................................308 Serial port error in 7-bit mode ...............................................309 SDRAM 256 MB mask failure ...................................................309 Erroneous timeouts when loading timer ....................................309 Station Address Logic: Multicast and broadcast packet filtering ........310 Station Address Logic: Unicast packets .....................................310 ...
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xii ...
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About the NS7520 his chapter provides an overview of the NS7520. The NS7520 is a high- performance, highly integrated, 32-bit system-on-a-chip ASIC designed for use in intelligent networked devices and Internet ...
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NS7520 Features The NS7520 can support most any networking scenario, and includes a 10/100 BaseT Ethernet MAC and two independent serial ports (each of which can ...
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General-purpose I/O pins – 16 programmable GPIO interface pins Four pins programmable with level-sensitive interrupt – Serial ports Two fully independent serial ports (UART, SPI) – Digital phase lock loop (DPLL) for receive clock extractions – 32-byte transmit/receive FIFOs – ...
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Programmable timers – Two independent timers (2μs–20.7 hours) Watchdog timer (interrupt or reset on expiration) – Programmable bus monitor or timer – Operating frequency 36, 46, ...
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NS7520 module block diagram Figure overview of the NS7520, including all the modules. PLL System Clock 3.3V Power 1.5V Figure 1: NS7520 overview Debugger JTAG Debug Interface FIRQ ARM7TDMI IRQ BBUS ...
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Operating frequency The NS7520 is available in grades operating at three maximum operating frequencies: 36 MHz, 46 MHz, and 55 MHz. The ...
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Pinout and Packaging NS7520 can be used in any embedded environment requiring networking services in an Ethernet LAN. The NS7520 contains an integrated ARM RISC processor, 10/100 Ethernet MAC, serial ...
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Packaging Table 1 provides the NS7520 packaging dimensions. Figure 2 shows the pinout and NS7520 dimensions. Figure 3 shows the NS7520 BGA layout. Symbol Min A — A1 0.35 A2 — ...
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PFBGA Figure 2: NS7520 pinout and dimensions ...
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D31 D30 D26 GNDPY1 A1 VCCPY4 D28 ...
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Pinout detail tables and signal descriptions Each pinout table applies to a specific interface and contains the following information: Column Description Signal The pin name for each I/O signal. Some signals have multiple function modes and are identified accordingly. The ...
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System ...
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Symbol Pin ADDR6 R2 U ADDR5 M4 U ADDR4 N4 U ADDR3 R1 U ADDR2 M3 U ADDR1 N2 U ADDR0 P1 U DATA31 N1 DATA30 M1 DATA29 L3 DATA28 L2 DATA27 L4 DATA26 L1 DATA25 K3 DATA24 K2 DATA23 ...
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Symbol ...
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Symbol Pin BG_ C7 BUSY_ B7 Table 2: System bus interface pinout Signal descriptions Mnemonic Signal BCLK Bus clock ADDR[27:0] Address bus DATA[31:0] Data bus TS_ Transfer start BE_ Byte enable TA_ Transfer acknowledge Table 3: System bus interface signal ...
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Mnemonic ...
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Symbol Pin CAS1_ B3 CAS0_ A2 WE_ C6 OE_ B6 Table 4: Chip select controller pinout Signal descriptions Mnemonic Signal CS0_ Chip select 0 CS1_ Chip select 1 CS2_ Chip select 2 CS3_ Chip select 3 CS4_ Chip select 4 ...
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Mnemonic ...
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Symbol Pin RXD2 GP input B15 RXD1 GP input A15 RXD0 RXD B13 RXER GP input C15 RXDV GP input D15 Table 6: Ethernet interface MAC pinout Signal descriptions The Ethernet MII (media independent interface) provides the connection between the ...
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Mnemonic ...
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Pin Description R13 Add a 15K ohm pulldown to GND (15K ohm is the recommended value; 10– 20K ohms is acceptable) P12 Add a 15K ohm pulldown to GND (15K ohm is the recommended value; 10– 20K ...
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GPIO ...
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GPIO Serial Other signal signal signal 2 PORTC1 CTSB_ LIRQ1/ DONE2_ (O) 2 PORTC0 TXCB/ LIRQ0/ OUT2B_/ DONE2_(I) DCDB_ Table 9: GPIO pinout Notes: RESET output indicates the reset state of the NS7520. PORTC4 persists beyond 1 the negation of ...
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System ...
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This figure shows the timing and specification for RESET_ rise/fall times max = 18ns Vin = 2.0V to 0.8V System mode (test support) PLLTST_, BISTEN_, and SCANEN_ primary inputs control different test modes for both functional and manufacturing ...
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JTAG ...
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Mnemonic Signal TRST_ Test mode reset TCK Test mode clock Table 14: ARM debugger signal description Figure 4: TRST_ termination Description TRST_ ...
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Power ...
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Working with the CPU CPU uses an ARM7TDMI core processor, which provides high performance while maintaining low power consumption and small size. This chapter describes the ARM Thumb concept and ...
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ARM Thumb concept The ARM7TDMI processor uses a unique architectural strategy known as Thumb, which makes the processor ideally suited to high-volume applications with memory ...
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The ARM instruction set yields a 0.9 Dhrystone (2.1) rating MIPS/MHz of instruction executions; the Thumb instruction set yields 0.75 Dhrystones MIPS/MHz. The MHz rating reflects the rate at which instructions can be fetched from external flash memory, as shown ...
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Summary of ARM exceptions The ARM processor can be interrupted by any of seven basic exceptions: ...
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Not all exceptions can occur at the same time, however. Undefined instructions and SWIs are mutually exclusive, as they each correspond to particular (non-overlapping) decoding of the current instruction data abort occurs at the same time as FIRQ ...
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All internal ARM7TDMI internal peripherals are presented to the CPU using the IRQ or FIRQ interrupt ...
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After emulating the failed instruction, the trap handler should execute the following instruction irrespective of the state (Thumb or ARM): This instruction restores the PC and CPSR, and returns to the instruction following the undefined instruction. SWI exception An SWI ...
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The abort mechanism allows the implementation of a demand-paged virtual memory system. In this type of ...
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Entering and exiting an exception (software action) The ARM7TDMI performs specific steps when handling exceptions. Entering an exception When handling an exception, ARM7TDMI does this: Preserves the address of the next instruction in the appropriate Link register the ...
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explicit switch back to Thumb state is never needed. Restoring the Note: CPSR from the ...
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Hardware Interrupts Two wires that go into the ARM7 CPU core can interrupt the processor: IRQ (normal interrupt) FIRQ (fast interrupt) Although the interrupts are basically the same, FIRQ can interrupt IRQ. FIRQ and IRQ lines The FIRQ line adds ...
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Interrupt Status Register Enabled. Identifies the current state of all interrupt sources that are enabled. This register is defined by performing a ...
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PORTC interrupts. The lower four pins of PORTC (C3, C2, C1, C0) on the ARM7TDMI can be used as interrupt sources. Only the PORTC register enables, configures, and services the interrupts. See Chapter 6, "GEN Module." ...
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BBus Module his chapter describes the BBus module, which provides the data path between NS7520 internal modules. Additional BBus functionality includes: Address and multiplexing logic that supports the data flow through ...
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BBus masters and slaves The BBus module consists of bus master and bus slave modules. The BBus state machine allows ...
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Address decoding The CPU address map is divided to allow access to the internal modules and external resources routed through the internal peripherals. Each slave module is given a small portion of the system address map for configuration and status. ...
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SYS Module SYS module provides the NS7520 with its system clock reset resources. (SYS_RESET and system (SYS_CLK ...
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Signal description The system control signals determine the basic operation of the chip: Signal mnemonic {XTALA1, XTALA2} {PLLVDD, PLLVSS} RESET_ {TDI, TDO, TNS, ...
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BISTEN_, mode hardware configuration," beginning on page 50. System clock generation (NS7520 clock module) The NS7520 clock module creates the BCLK and FXTAL signals. Both signals are used internally, but BCLK can also be accessed at ball A6 ...
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NS7520 clock module block diagram This diagram provides an overview of the clock module. ...
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The clock module has two power pins: PLLVDD and PLLVSS. PLLVDD is connected to 1.5 volts PLLVSS is connected to ground The PLLTST* input is connected to ground to use boundary scan testing connected to 3.3 volts through ...
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PLL mode hardware configuration Figure 5, "PLL mode hardware configuration," on page 53, shows how the crystal is connected to the XTALA1 ...
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The NS7520 address bus has internal pullups. 2.7K pulldown resistors can be connected to the address lines to configure the PLL settings at bootup. Move jumpers here for boundary scan mode only. Place jumpers here for normal/debug mode. MAX811 ...
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Setting the PLL frequency Three fields — IS (charge pump current), FS (output divider), and ND (PLL multiplier) ...
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Bits Access Mnemonic D08:07 Read IS only D06:05 Read FS only D04:00 Read ND only Table 21: PLL Settings register bit definition The next table shows the 32 frequencies that can be produced with an 18.432MHz crystal ...
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MHz A[8:7] 23.0 00 27.6 00 32.3 00 36.9 00 41.5 11 46.1 11 50.7 11 55.3 11 ...
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... Notes: Digi guarantees that the NS7520B-1-C36 will work at all frequencies 36.9MHz. Digi guarantees that the NS7520B-1-C46 will work at all frequencies 46.1MHz. Digi guarantees that the Ns7520B-1-C55 will work at all frequencies 55.3MHz. 55.3MHz is the default frequency when address lines A[8:0] are not adjusted 4 with pulldown resistors ...
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PLL frequency. The NS7520 resets whenever the PLLCNT field is changed, then starts running at the new frequency ...
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... Digi guarantees that the NS7520B-1-C36 will work at all frequencies 36.9MHz. Digi guarantees that the NS7520B-1-C46 will work at all frequencies 46.1MHz. Digi guarantees that the Ns7520B-1-C55 will work at all frequencies 55.3MHz. Reset circuit sources There are three reset circuit sources: external, watchdog, and software. ...
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Address bit Name ADDR[27] Endian configuration ADDR[26] CPU bootstrap ADDR[24:23] CS0/MMCR[19:18] ...
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GEN Module The GEN module provides the NS7520 with its main system control functions, as well as the following: Two programmable timers with interrupt One programmable bus-error timer One programmable watchdog timer ...
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Module configuration The GEN module is configured as shown: Address FFB0 0000 FFB0 0004 FFB0 000C FFB0 0010 FFB0 0014 FFB0 ...
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GEN module registers All registers are 32 bits unless otherwise noted. System Control register Address: FFB0 0000 General information All bits in the System Control register are active high unless an underscore (_) appears in the signal name; the underscore ...
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Bits Access D24 R/W D23:22 R/W D21:20 R/W D19 N/A D18 R/W Table 24: System Control register bit definition ...
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Bits Access Mnemonic D17:16 R/W BMT D15 R/W USER D14 R/W BUSER D13 N/A Reserved Table 24: System Control register bit definition Reset Description 0 Bus monitor timer Controls the timeout period for the bus monitor timer: 00 128 BCLKs ...
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Bits Access D12 R/W D11 R/W D10 R/W D09:08 N/A D07 R/W D06 R/W Table 24: System Control register bit definition 6 ...
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Bits Access Mnemonic D05:04 R/W BSYNC D03:00 N/A Reserved Table 24: System Control register bit definition Reset Description 0 TA_ input synchronizer Defines the level of synchronization performed within the NS7520 for TA_ input: 00 1-stage synchronizer 01 1-stage synchronizer ...
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System Status register Address: FFB0 0004 All bits in the System Status register, except EXT, WDOG, PLL, and SOFT, are loaded during ...
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Bits Access D22 R/C D21 R/C D20 R/C D19:11 N/A D10:00 R/O Table 25: System Status register bit definition Software Service register Address: FFB0 000C Mnemonic Reset Description WDOG N/A Last reset caused by watchdog timer When set to 1, ...
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The Software Service register (SWSR) acknowledges the system watchdog timer so, firmware must write operations. There is no restriction on ...
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TIMEOUT = [4096 * ( TIMEOUT = ( SYSCLK TIE TIRO TPRE TCLK Register bit definition Bits Access Mnemonic ...
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Bits Access D27 R/W D26:00 R/W Table 27: Timer Control registers bit definition ...
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Timer Status registers Address: FFB0 0014 / FFB0 001C Rsvd TIP Reserved Register bit assignment Bits Access D31 N/A D30 R/C D29:27 N/A D26:00 R Table 28: Timer Status registers bit definition PORTA Configuration ...
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The PORTA register configures the PORTA general-purpose input/output (GPIO) pins. Each of the PORTA GPIO pins can be individually programmed — as ...
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Bits Access Mnemonic D07:00 R/W ADATA Table 29: PORTA register bit definition PORTA Configuration The ADIR and AMODE bits together provide independent configuration of each pin. Each column in this table denotes one of the possible configurations for each bit. ...
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PORTA AMODE=0 bit ADIR=0 PORTA1 GPIO IN PORTA0 GPIO IN Table 30: PORTA configuration Inputs An input that provides one or more ...
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PORTC Configuration register Address: FFB0 0028 The PORTC register configures the PORTC general-purpose input/output (GPIO pins). Each of the PORTC GPIO pins can be individually programmed — as general-purpose input or output, or special function input or output — as ...
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Bits Access D07:00 R/W Table 31: PORTC register bit definition PORTC configuration The CSF, CDIR, and CMODE bits together provide independent configuration ...
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PORTC bit CMODE=0 CDIR=0 CDIR=1 PORTC0 GPIO IN GPIO OUT PORTC bit CMODE=0 CDIR=0 CDIR=1 PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 DONE2_IN_ Table 32: PORTC configuration Inputs An input that provides one or more input signals to different ...
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READBACK When reading the CDATA field, the data read depends on how the pin is configured: Configured as GPIO output. Reads data from the register whose data drives the pin. ...
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Interrupts come from different sources on the chip and are managed with Interrupt Control registers. Interrupts can be enabled/disabled on a per-source basis using the Interrupt Enable registers. These registers serve as masks for the different interrupt sources. Interrupt controller ...
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Bits Access D31:19 R/W D18 N/A D17 R/W D16 R/W D15 R/W D14 R/W D13 R/W D12 R/W D11:08 N/A D07 R/W D06 R/W D05 R/W D04 R/W D03 R/W ...
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...
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Memory Controller Module memory (MEM) module provides a glueless interface to external memory devices such as flash, DRAM, and EEPROM. The memory controller contains an integrated DRAM controller, and supports ...
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About the MEM module The MEM module monitors the BBus interface for access to the BUS module; that is, any access not addressing ...
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Chip select configured for SRAM. The MEM module controls the CS[4:0]_, OE_, and WE_ signals. The address from the current bus master is driven directly to A[27:0]. Chip select configured for FP or EDO DRAM. The MEM module can be ...
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Address FFC0 0000 FFC0 0010 FFC0 0014 FFC0 0018 FFC0 0020 FFC0 0024 FFC0 0028 FFC0 0030 FFC0 ...
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the MASK field indicates that the associated address ignored in the address decoding process. When accessing a static memory device, the maximum value of the base Note: address is To determine whether a BBus ...
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The software reset command issued by the GEN module Software Service Note: register has no effect on any ...
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Bits Access Mnemonic D20 R/W AMUX D19 R/W A[27] D18 R/W A[26] D17 R/W A25 Table 36: MMCR bit definition ...
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Bits Access D16 R/W D15:00 N/A Table 36: MMCR bit definition A27 and A26 bit settings The A27 ...
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BASE PGSIZE Bits Access Mnemonic D31:12 R/W BASE D11:10 R/W PGSIZE Table 37: Chip Select Base Address register bit definition ...
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Bits Access D09:08 R/W D07 R/W D06 R/W Table 37: Chip Select Base Address register bit definition 9 ...
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Bits Access Mnemonic D05 R/W DMUXM D04 R/W IDLE D03 R/W DRSEL D02 R/W BURST D01 R/W WP Table 37: Chip Select Base Address register bit definition ...
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Bits Access D00 R/W Table 37: Chip Select Base Address register bit definition ...
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Chip Select Option Register A Address: FFC0 0014/24/34/44/54 The Chip Select Option Register A defines the physical size of the chip select, as well as other features. Each chip select can be configured in size from 4 Kbytes to 4 ...
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Bits Access WAIT[3:0]/BCYC[1:0] continued Table 38: Chip Select Option Register A bit definition ...
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Bits Access Mnemonic WAIT[3:0]/BCYC[1:0] continued D05:04 R/W BSIZE D03:02 R/W PS Table 38: Chip Select Option Register A bit definition ...
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Bits Access D01 R/W D00 R/W Table 38: Chip Select Option Register A bit definition ...
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Chip Select Option Register B Address: FFC0 0018/28/38/48/ Bits Access D31:06 N/A D05:04 R/W D03:02 R/W Table 39: Chip Select Option Register B bit definition Reserved 12 11 ...
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Bits Access D01:00 R/W Table 39: Chip Select Option Register B bit ...
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BCLK ADDR BEn_ CS0_ CS1_ R/W_ WE_ OE_ DATA TA_ Sync Write Figure 6: Synchronous SRAM cycles All outputs change state relative to the rising edge of BCLK with the exception of OE_ and WE_, which ...
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BCLK ADDR BEn_ CS0_ CS1_ R/W_ WE_ OE_ DATA TA_ ...
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T1 BCLK CS_ ADDR[31:4] 000 ADDR[3:1] R/W_ WE_ OE_ BE0_ BE1_ DATA TA_ Figure 8: SRAM synchronous burst read cycle NS7520 DRAM address multiplexing The NS7520 can be configured to use an internal DRAM address multiplexer or an external address ...
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When a particular DRAM has less than 14 address bits, use ...
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NS7520 multiplexed address outputs NS7520 pin A13 A12 A11 DRAM pin A9 RAS 18 CAS 19 8-bit DRAM peripheral (20 address bits: 10 RAS and 10 CAS) NS7520 pin A13 A12 A11 DRAM pin A9 RAS 19 CAS 20 16-bit ...
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NS7520 multiplexed address outputs NS7520 A23 A22 A13 A12 pin DRAM ...
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Setting the DMUXS bit indicates that the internal address multiplexer must be disabled when the specific chip select is activated. The NS7520 drives the address bus using standard addressing without any multiplexing, but only for the specific chip select, the ...
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Normal and burst (FP/EDO) cycles Programmable wait states for normal (also first cycle ion burst access) and burst cycles Programmable ...
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FP/EDO DRAM burst cycles The DRAM controller supports both read and write burst cycles. A DRAM Burst cycle must operate with a minimum of one wait state for the first cycle and a minimum of two BCLK cycles in subsequent ...
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NS7520 SDRAM interconnect The NS7520 can interconnect to standard 16Mb and 64Mb SDRAM components, using x32, x16, and x8 SDRAM configuration. You can use 128Mb components in the x32 configuration, but not in the x8 ...
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SDRAM signal components NS7520 signal 16 Mb (1Mx16 A10 A8 A11 A9 A12 A13 A21 BA A22 A23 BCLK CLK VCC CKE D31-D16 ...
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NS7520 signal CS/RAS_ CAS3_ CAS2_ CAS1_ CAS0_ BE3_ BE2_ BE1_ BE0_ A10 A11 A12 A13 A20 A21 Table 43: x16 SDRAM interconnect ...
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NS7520 signal 16M SDRAM signal A22 BCLK CLK VCC CKE D31-D16 D15-D00 Table 43: x16 SDRAM interconnect x8 SDRAM configurations Table 44 identifies the interconnect between the NS7520 and SDRAM when SDRAM is used configuration ...
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NS7520 signal A10 A11 A13 A19 A20 A21 BCLK VCC D31-D16 Table 44: x8 SDRAM interconnect SDRAM A10/AP support The SDRAM A10/AP signal multiplexes one of the RAS ...
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The NS7520 provides the A10/AP multiplexing function using the CAS0_ pin. During the active command, the CAS0_ pin is driven with the logical value of one of the address bits A[21:18 function of the port size configuration defined ...
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Command CSx_ Load mode 0 Table 45: SDRAM command definitions Memory timing fields — SDRAM The WAIT configuration in the Chip Select Option register provides the SDRAM T and T parameters. When WAIT is configured ...
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BSIZE Burst length 11 Full page The JEDEC SDRAM standard requires the SDRAM load mode command to set burst length to to recognize burst terminate commands. Not all SDRAMs require this full page setting. If you want to set burst ...
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SDRAM read cycles Figure 11 and Figure 12 provide timing examples for SDRAM normal and burst reads, respectively, with WAIT and BCYC configured with a value of 0. BCLK TS_ RW_ BE[3:0] D[31:0] CS[7:0]_ CAS3_(RAS_) ...
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BCLK TS_ RW_ BE[3:0] D[31:0] CS[7:0]_ CAS3_(RAS_) CAS2_(CAS_) CAS1_(WE_) A[13:0] AMUX TA_ {output} TEA_(LAST_) {output} TA_ {input} TEA_(LAST_) {input} Figure 12: SDRAM burst read The precharge command is issued, when necessary, during the T1 phase of a normal or ...
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wait states are inserted after the read command, depending on the value of the BCYC configuration. The BCYC configuration identifies the CAS latency specification for the SDRAM. The burst stop command is issued at the ...
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BCLK TS_ RW_ BE[3:0] D[31:0] CS[7:0]_ CAS3_(RAS_) CAS2_(CAS_) CAS1_(WE_) A[13:0] AMUX TA_ {output} TEA_(LAST_) {output} TA_ {input} TEA_(LAST_) {input} Figure 14: SDRAM burst write The precharge command is issued, when necessary, during the T1 phase of a normal or ...
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The write command is always issued during the T2 state since data is available only at that ...
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The memory controller does a normal access to address determine access timing. The memory controller then follows with 3 burst beats to address offsets , , and ’h10 ’h14 ’h18 The memory peripheral properly delivers the data at address offset ...
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...
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DMA Module NS7520 supports 13 DMA channels. Each channel moves blocks of data between memory and a memory peripheral. Each block transfer is defined by a descriptor of two words ...
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DMA module Each DMA controller has a state machine and a block of static RAM referred to as context RAM. The context RAM contains the current state of each DMA channel. ...
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BBus and provides the external address for a single data transfer operation. Figure 16 provides a simple representation of DMA fly-by mode: Memory Address Data Figure 16: ...
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DMA buffer descriptor All DMA channels operate using a buffer descriptor. Each DMA channel remains idle until enabled using the CE ...
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Buffer descriptor bit definitions Bit Description W Wrap bit. When set (W=1), tells the DMA controller that this is the last buffer descriptor within the continuous list of descriptors. The next buffer descriptor is found using the initial DMA channel ...
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Buffer descriptor field definitions Field Source buffer pointer/Buffer pointer Status Buffer length: Peripheral-to- memory Buffer length: Memory-to- peripheral Buffer ...
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FB write indicates fly-by peripheral-to-memory. FB read indicates fly-by memory-to-peripheral. MM indicates memory-to-memory. DMA channels 3/5 and 4/6 can interface with external peripheral devices using DMA handshake signals multiplexed through the GPIO pins in PORTA and PORTC. Channel Base address ...
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The DMA Control register should be written to enable the DMA channel only after all other registers and descriptors are valid. ...
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Address Description FF90 00114 DMA 6 Status register FF90 0120 DMA 7 Buffer Descriptor Pointer register FF90 0130 DMA 7 Control register FF90 0134 DMA 7 Status register FF90 0140 DMA 8 Buffer Descriptor Pointer register FF90 0150 DMA 8 ...
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Buffer Descriptor Pointer register Address: FF90 0000 / ...
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Bits Access Mnemonic D30 W CA D29:28 R/W BB D27:26 R/W MODE Table 50: DMA Control register bit definition Reset Description 0 Channel abort request When set, causes the current DMA operation to complete and the buffer to be closed. ...
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Bits Access D25:24 R/W Table 50: DMA Control register bit definition ...
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Bits Access Mnemonic BTE continued D23 R/W REQ Table 50: DMA Control register bit definition Reset Description The DMA delivers to the destination peripheral the same number of bytes read from the source peripheral, regardless of whether the destination peripheral ...
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Bits Access REQ continued D22 N/A D21 R/W D20 R/W D19:18 N/A Table 50: DMA Control register bit definition 1 4 ...
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Bits Access Mnemonic D17:16 R/W SIZE D15:10 R STATE D09:00 R INDEX Table 50: DMA Control register bit definition Reset Description 0 Data operand size 00 32 bit 01 16 bit 10 8 bit 11 Reserved Used to define the ...
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DMA Status/Interrupt Enable register Address: FF90 0014 / ...
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Bits Access Mnemonic D29 R/C NRIP D28 R/C CAIP D27 R/C PCIP D26:25 N/A Reserved D24 R/W PCIE D23 R/W NCIE D22 R/W ECIE D21 R/W NRIE Table 51: DMA Status/Interrupt Enable register bit definition Reset Description 0 Buffer not ...
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Bits Access D20 R/W D19 R D18 R D17 R ...
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In general, the problem of transmit underruns can be avoided by running in half duplex rather than full duplex. Late collisions can be eliminated by proper network design; late collisions are caused by too many cascaded levels of hubs, switches, ...
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Because interrupts are set when DMA channel 1 encounters buffers that are ...
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Signal description Signal Description DREQ_ An input to the NS7520, sourced by the external device. All transfers are initiated when the external device asserts DREQ_ low. When the external device wants a DMA transfer (either read or write), it asserts ...
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NS7520 DREQ_ DACK_ DONE_ R/W_ DATA[31:0] ADDR[27:0] CSx_ CSx_ Memory CS_ ADDR[X:0] DATA{ 31:0] R/W_ Figure 20: Hardware needed for external memory-to-memory ...
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Ethernet Module Ethernet controller module provides the NS7520 with one IEEE 802.3u compatible Ethernet interface. Two modules comprise the Ethernet interface: the Ethernet front-end (EFE) and the media access controller ...
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Ethernet front-end (EFE) Figure 21 shows a high-level block diagram of the EFE module. The EFE module provides ...
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EFE logic provides all control and status registers required by the Ethernet module. The transmitter and receiver each provide a 16-bit status word after processing each Ethernet frame. These status words can be given to the CPU on an interrupt ...
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The MAC forwards good Ethernet packets through address filtering. Packets can be filtered based on station address, broadcast, ...
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Interrupts are set when the DMA channel encounters buffers that are not ready. The device driver should be designed with the smallest buffers in the A pool and the largest buffers in the D pool. The number of available pools ...
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MAC module The MAC component of the NS7520 provides a full function 10/100 Mbps media access controller module with media independent interface (MII) and optional interface modules, which include MII, PMD, ...
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MAC core EFE MCS TFUN Host RFUN HOST Figure 23: MAC block diagram Other modules in the diagram include: MAC core — 10/100 Mbps media access controller. Performs the CSMA/CD function and flow control functions. See ISO/IEC and IEEE Standard ...
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DMA channel assignments One DMA channel is dedicated to Ethernet receive and one DMA channel is dedicated to Ethernet ...
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Address Register FF80 0414 MAXF FF80 0418 SUPP FF80 041C TEST FF80 0420 MCFG FF80 0424 MCMD FF80 0428 MADR FF80 042C MWTD FF80 0430 MRDD FF80 0434 MIND FF80 0438 SMII FF80 0440 SA1 FF80 0444 SA2 FF80 0448 ...
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Ethernet General Control register (EGCR) bit definitions Address: FF80 0000 General information These fields should be set only once, on device open: ERX ERXDMA ...
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Bits Access Mnemonic D31 R/W ERX D30 R/W ERXDMA D29 R/W ERXLNG D28 R/W ERXSHT D27 R/W ERXREG D26 R/W ERFIFOH D25 R/W ERXBR D24 R/W ERXBAD Table 53: Ethernet General Control register bit definition Reset Description 0 Enable receive ...
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Bits Access D23 R/W D22 R/W D21:20 R/W D19 R/W D18 R/W D17 R/W Table 53: Ethernet General Control register bit definition 1 6 ...
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Bits Access Mnemonic D16 R/W EFULLD D15:14 R/W MODE D13 N/A Reserved D12 R/W RXCINV D11 R/W TXCINV D10 R/W pNA Table 53: Ethernet General Control register bit definition Reset Description 0 Enable full-duplex operation Set allow ...
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Bits Access D09 R/W D08 R/W D07:02 R/W D01:00 R/W Table 53: Ethernet General Control register bit definition ENDEC mode and NS7520 pins Table ...
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MODE field Output based on EFE CSR bit Not ‘b00 TXD1=PDN inverted, open drain Not ‘b00 TXD2=AUI_TP[1] Not ‘b00 TXD3=AUI_TP[0] Not ‘b00 TXER=LNK_DIS_ Not ‘b00 and not ‘b11 MDC=LPBK ‘b11 MDC=LPBK inverted Not ‘b00 MDO=UTP_STP Table 54: ENDEC control signal ...
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Ethernet General Status register (EGSR) bit definitions Address: FF80 0004 General information These fields are used only when using Ethernet receive in interrupt service ...
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Bits Access Mnemonic D29:28 R RXFDB D27 R RXREGR D26 R RXFIFOH D25 R/C RXBR D24 R/W RXSKIP Table 55: Ethernet General Status register bit definition Reset Description 0 Receive FIFO data available Valid only when RXREGR (D27 ...
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Bits Access D23:20 N/A D19 R D18 R D17 R/C D16 R D15:10 R D09:00 N/A Table 55: Ethernet General Status register bit definition ...
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Data bit NS7520 pin D15 RXD2 D13 RXD1 D12 RXD3 D11 RXER D10 RXDV Table 56: ENDEC status signal cross-reference Ethernet FIFO Data register Address: FF80 0008 / FF80 000C (secondary address) The Ethernet FIFO Data register allows manual interface ...
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The Ethernet Receive Status register (see "Ethernet Receive Status Note: register" on page 173) should be read before clearing the RXBR bit. When operating ...
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General Status register when a transmit frame is completed and the Ethernet Transmit Status register is loaded. The lower 16 bits (D15:00) of the register are also loaded into the StatusOrIndex field of the DMA buffer descriptor when using DMA ...
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Bits Access D12 R D11 R D10 R Table 58: Ethernet Transmit Status register bit definition ...
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Bits Access Mnemonic D09 R TXAUR D08 R TXAJ D07 N/A Not used Table 58: Ethernet Transmit Status register bit definition Reset Description 0 Transmit aborted — underrun Set indicate that the last Ethernet packet was not ...
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Bits Access D06 R D05 R D04 N/A D03:00 R Table 58: Ethernet Transmit Status register bit definition ...
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Ethernet Receive Status register Address: FF80 0014 The Ethernet Receive Status register contains the status for the last completed receive buffer. The receive buffer complete bit (RXBR) is set in the Ethernet General Status register when a receive frame is ...
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Bits Access D14 R D13 R D12 R D11 R Table 59: Ethernet Receive Status register bit definition ...
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Bits Access Mnemonic D10 R RXCRC D09 R RXDR D08 R RXCV D07 R RXLNG D06 R RXSHT Table 59: Ethernet Receive Status register bit definition Reset Description 0 Receive packet has CRC error Set indicate that ...
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Bits Access D05 R D04:00 N/A Table 59: Ethernet Receive Status register bit definition MAC Configuration Register 1 Address: FF80 0400 MAC Configuration Register ...
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Register bit assignment Bits Access Mnemonic D31:16 N/A Reserved D15 R/W SRST D14 R/W SIMRST D13:12 N/A Reserved D11 R/W RPEMCSR D10 R/W RPERFUN D09 R/W RPEMCST D08 R/W RPETFUN D07:05 N/A Reserved D04 R/W LOOPBK D03 R/W TXFLOW Table ...
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Bits Access D02 R/W D01 R/W D00 R/W Table 60: MAC Configuration Register 1 bit definition MAC Configuration Register 2 Address: FF80 0404 MAC ...
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Register bit assignment Bits Access Mnemonic D31:15 N/A Reserved D14 R/W EDEFER D13 R/W BACKP D12 R/W NOBO D11:10 N/A Reserved D09 R/W LONGP D08 R/W PUREP Table 61: MAC Configuration Register 2 bit definition Reset Description N/A N/A 0 ...
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Bits Access D07 R/W D06 R/W D05 R/W D04 R/W D03 R/W D02 R/W Table 61: MAC Configuration Register 2 bit definition 1 8 ...
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Bits Access Mnemonic D01 R/W FLENC D00 R/W FULLD Table 61: MAC Configuration Register 2 bit definition Pad operation table This table provides a description of the pad function based on the configuration of the AUTOP field. Type AUTOP VLANP ...
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Back-to-Back Inter-Packet-Gap register Address: FF80 0408 Register bit assignment Bits Access D31:07 N/A D06:00 R/W Table 63: Back-to-Back ...
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Non-Back-to-Back Inter-Packet-Gap register Address: FF80 040C Rsvd Register bit assignment Bits Access D31:15 N/A D14:08 R/W D07 N/A D06:00 R/W Table 64: Non-Back-to-Back Inter-Packet-Gap register bit definition Reserved ...
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Collision Window/Collision Retry register Address: FF80 0410 Reserved Register bit assignment Bits Access D31:14 N/A D13:08 R/W D07:04 ...
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Maximum Frame register Address: FF80 0414 Register bit assignment Bits Access D31:16 N/A D15:00 R/W Table 66: Maximum Frame register bit definition Reserved ...
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PHY Support register Address: FF80 0418 Register bit assignment Bits Access D31:08 N/A D07 R/W D06 R/W D05 ...
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Bits Access D02 N/A D01 R/W D00 R/W Table 67: PHY Support register bit assignment Test register Address: FF80 041C Register bit assignment Bits Access D31:03 N/A Table 68: Test register bit definition Mnemonic ...
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Bits Access D02 R/W D01 R/W D00 R/W Table 68: Test register bit definition ...