NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 182

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1 7 0
E F E c o n f i g u r a t i o n
Table 58: Ethernet Transmit Status register bit definition
D12
D11
D10
Bits
R
R
R
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
TXAL
TXAED
TXAEC
Mnemonic
0
0
0
Reset
Transmit abort — late collision
Set to 1 to indicate that the last Ethernet packet was not
transmitted successfully; packet transmission was aborted
due to a late collision problem.
When this bit is set, the transmit frame is automatically
flushed from the transmit FIFO. TXREGE and TXFIFOH
in the Ethernet General Status register become active when
the FIFO is ready to start receiving the next packet.
TXBC in the Ethernet General Status register becomes
active when TXAL is set.
Transmit abort — excessive deferral
Set to 1 to indicate that the last Ethernet packet was not
transmitted successfully; packet transmission was aborted
due to excessive deferral. Excessive deferral means that
there was a receive carrier on the Ethernet channel for a
long period of time, making it impossible for the
transmitter to try to transmit.
When this bit is set, the transmit frame is automatically
flushed from the transmit FIFO. TXREGE and TXFIFOH
in the Ethernet General Status register become active when
the FIFO is ready to start receiving the next packet.
TXBC in the Ethernet General Status register becomes
active when TXAED is set.
Transmit abort — excessive collisions
Set to 1 to indicate that the last Ethernet packet was not
transmitted successfully; packet transmission was aborted
due to an excessive number of collisions. The maximum
number of collisions allowed is determined by the RETRY
field in the Collisions Window/Collision Retry register.
When this bit is set, the transmit frame is automatically
flushed from the transmit FIFO. TXREGE and TXFIFOH
in the Ethernet General Status register become active when
the FIFO is ready to start receiving the next packet.
TXBC in the Ethernet General Status register becomes
active when TXAEC is set.
Description