NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 168
NS7520B-1-C36
Manufacturer Part Number
NS7520B-1-C36
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Specifications of NS7520B-1-C36
Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NS7520B-1-C36
Manufacturer:
Digi International
Quantity:
10 000
Part Number:
NS7520B-1-C36
Manufacturer:
NETARM
Quantity:
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D M A c h a n n e l a s s i g n m e n t s
DMA channel assignments
EFE configuration
One DMA channel is dedicated to Ethernet receive and one DMA channel is dedicated
to Ethernet transmit. The Ethernet receiver has four DMA subchannels, which support
the receive buffer descriptor selection feature (see "DMA buffer descriptor,"
beginning on page 130).
Table 52 shows the Ethernet front-end register map. All registers are 32 bits unless
otherwise noted.
Note:
Table 52: EFE register map
FF80 0000
FF80 0004
FF80 0008
FF80 000C
FF80 0010
FF80 0014
FF80 0400
FF80 0404
FF80 0408
FF80 040C
FF80 0410
Address
The Ethernet receiver is assigned DMA channel 1 (1A, 1B, 1C, and 1D).
The Ethernet transmitter is assigned DMA channel 2.
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Reading or writing the MAC configuration registers (address locations
0xFF80 0400 through 0xFF80 05DC) is unreliable without valid clocks on
the TXCLK and RXCLK input pins.
EGCR
EGSR
FIFO
FIFOL
ETSR
ERSR
MAC1
MAC2
IPGT
IPGR
CLRT
Register
Ethernet General Control register
Ethernet General Status register
Ethernet FIFO Data register
Ethernet FIFO Data Register Last
Ethernet Transmit Status register
Ethernet Receive Status register
MAC Configuration Register 1
MAC Configuration Register 2
Back-to-Back Inter-Packet-Gap register
Non-Back-to-Back Inter-Packet-Gap register
Collision Window/Retry register
Register description
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