NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 179

no-image

NS7520B-1-C36

Manufacturer Part Number
NS7520B-1-C36
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Datasheets

Specifications of NS7520B-1-C36

Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NS7520B-1-C36
Manufacturer:
Digi International
Quantity:
10 000
Part Number:
NS7520B-1-C36
Manufacturer:
NETARM
Quantity:
20 000
Ethernet FIFO Data register
Table 56: ENDEC status signal cross-reference
Address: FF80 0008 / FF80 000C (secondary address)
The Ethernet FIFO Data register allows manual interface with the Ethernet FIFO,
rather than using DMA support. This register is used primarily as a diagnostic tool.
Writing to the Ethernet FIFO Data register
Writing to the Ethernet FIFO Data register loads the transmit FIFO. This register can
be written only when the TXREGE bit is set in the Ethernet General Status register,
indicating that space is available in the transmit FIFO.
The transmit FIFO has a secondary address
transmit frame. The first and middle words must use the primary address
(FF80 0008)
Writing to the secondary address with the transmit interrupts disabled (ETXBC in the
Ethernet General Control register) initiates transmission of data from the transmit
FIFO. Otherwise, transmission begins when the TX FIFO byte count equals the
selected watermark (ETXWM in the Ethernet General Control register).
Reading from the Ethernet FIFO Data register
Reading from the Ethernet FIFO Data register empties the receive FIFO. The Ethernet
General Status register indicates how many bytes are available to be read. The
receive FIFO is available only when the RXBR bit has been set to 1, which clears the
bit, in the Ethernet General Status register.
D15
D13
D12
D11
D10
Data bit
.
RXD2
RXD1
RXD3
RXER
RXDV
NS7520 pin
(FF80 000C)
w w w . d i g i e m b e d d e d . c o m
that signifies the last word of a
E t h e r n e t M o d u l e
1 6 7

Related parts for NS7520B-1-C36