NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 186

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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E F E c o n f i g u r a t i o n
Table 59: Ethernet Receive Status register bit definition
D14
D13
D12
D11
Bits
R
R
R
R
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
RXDV
RXOK
RXBR
RXMC
Mnemonic
0
0
0
0
Reset
Receive data violation event previously seen
Set to 1 to indicate that, at some point since the last
recorded receive packet, a receive data violation was
detected, noted, and reported with this receive packet
event. The receive data event is not associated with this
particular packet.
A receive data violation event occurs when there is no valid
preamble and start frame delimiter (SFD) in the data
stream.
Receive packet OK
Set to 1 to indicate that the next packet in the receive FIFO
has been received without any errors.
When this bit is set, the RXREGR and RXFIFOH bits in
the Ethernet General Status register become active and the
packet can be emptied (using interrupts, polling, or DMA).
When the packet has been emptied, RXREGR and
RXFIFOH become inactive until the next receive buffer is
ready.
Receive broadcast packet
Set to 1 to indicate that the next packet in the receive FIFO
is a broadcast packet.
When this bit is set, the RXREGR and RXFIFOH bits in
the Ethernet General Status register become active and the
packet can be emptied (using interrupts, polling, or DMA).
When the packet has been emptied, RXREGR and
RXFIFOH become inactive until the next receive buffer is
ready.
Receive multicast packet
Set to 1 to indicate that the next packet in the receive FIFO
is a multicast packet.
When this bit is set, the RXREGR and RXFIFOH bits in
the Ethernet General Status register become active and the
packet can be emptied (using interrupts, polling, or DMA).
When the packet has been emptied, RXREGR and
RXFIFOH become inactive until the next receive buffer is
ready.
Description