NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 201

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MII Management Configuration register
Address: FF80 0420
Register bit assignment
Table 69: MII Management Configuration register bit definition
D31:16
D15
D14:05
D04:02
D01
D00
Bits
RMIIM
15
31
30
14
N/A
R/W
N/A
R/W
R/W
R/W
Access
29
13
28
12
Reserved
RMIIM
Reserved
CLKS
SPRE
SCANI
Mnemonic
27
11
26
10
Reserved
N/A
0
N/A
N/A
0
0
Reset
25
9
24
8
Reserved
N/A
Reset MII management
Set this bit to 1 to reset the MII management module.
N/A
Clock select
Used by the clock divide logic when creating the MII
management clock (MDC pin). The IEEE 802.3u standard
requires that the clock be no faster than 2.5 MHz. See
Table 70: "CLKS field settings" on page 190 for examples.
Note:
Suppress preamble
1
0
Note:
Scan increment (single scan for read data)
When set to 1, the MII management module performs read
cycles across a range of PHY devices, from address 1
through the value set in the RADR field in the MII Address
register (see page 192).
Description
w w w . d i g i e m b e d d e d . c o m
The MII management module performs read/write
cycles without the 32-bit preamble field.
Normal cycles are performed.
23
7
Some PHY devices support clock rates up to
12.5 MHz.
Some PHY devices support suppressed
preamble.
22
6
21
5
20
4
CLKS
19
3
E t h e r n e t M o d u l e
18
2
SPRE
17
1
SCANI
16
0
1 8 9