NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 71

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset circuit sources
NS7520 bootstrap initialization
1
2
3
There are three reset circuit sources: external, watchdog, and software.
Many internal NS7520 features are configured when the RESET pin is asserted. The
address bus configures the appropriate control register bits at powerup. (See also
"External oscillator mode hardware configuration," beginning on page 50.)
Digi guarantees that the NS7520B-1-C36 will work at all frequencies up to
36.9MHz.
Digi guarantees that the NS7520B-1-C46 will work at all frequencies up to
46.1MHz.
Digi guarantees that the Ns7520B-1-C55 will work at all frequencies up to
55.3MHz.
External reset. Powerup reset is initiated when the RESET_ input is
asserted low when power is applied. RESET_ should be driven low for at
least 40ms after power has reached safe operating levels, to allow external
crystals to start up. At other times, RESET_ must be one microsecond
minimum.
Watchdog reset. The watchdog reset is synchronous to SYS_CLK. A
hardware reset condition is triggered when the signal transitions from
active to inactive state.
Software reset. The CPU can also trigger a software reset by writing ‘h123
and ‘h321 to the Software Service register (see "Software Service register,"
beginning on page 69). Unless otherwise noted, configuration registers are
not reset by a software reset. When a software reset is triggered, the
appropriate modules are reset for a total of 16
w w w . d i g i e m b e d d e d . c o m
sys_clk
periods.
S Y S M o d u l e
5 9