NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 136

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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P e r i p h e r a l p a g e b u r s t s i z e
Peripheral page burst size
Note:
The peripheral device must provide a minimum burst page size of 64 bytes in order
for the NS7520 to support bursting to or from a memory peripheral device.
The NS7520 can begin a burst memory access on any address boundary. The NS7520
continues the burst until one of the following conditions is met:
The bus master can decide to terminate the burst at any time. The memory
controller limits the maximum number of bus cycles that can occur using the BSIZE
field. The memory controller also terminates the burst when a 64-byte page
boundary is encountered.
Example
The bus master begins a 16-byte burst cycle starting at
long words of data from address offsets
will allow the full burst because BSIZE allows a total of 16 long words to be accessed.
The write command is always issued during the T2 state since data is
available only at that time. If the precharge and active commands are not
required, a NOP is inserted in the T1 state of the write cycle.
The current bus master terminates the burst.
The memory controller terminates the burst because the number of bus
cycles for the burst cycle reached the maximum as defined in the BSIZE
field of the Chip Select Option register.
The current memory address has reached a 64-byte page boundary.
The memory peripheral is configured as a 32-bit peripheral.
The memory peripheral has a 16-byte page size.
The BSIZE field is set to the maximum value
16 bus cycles for each burst.
The bus master begins a 16-byte burst cycle starting with an address offset
of
’hC
.
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
This section applies only to internal TA and TEA.
’hC
,
’h10
,
’h14
11
, which implies a maximum of
, and
’hC.
’h18
It expects to receive four
. The memory controller