NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 174

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1 6 2
E F E c o n f i g u r a t i o n
Table 53: Ethernet General Control register bit definition
ENDEC mode and NS7520 pins
Table 54 shows the relationship between the lower bits in the Ethernet General
Control register and the NS7520 pins that they control. The NS7520 pins are
controlled by these bits only when the MODE field (D15:14) is set to ENDEC.
D09
D08
D07:02
D01:00
Bits
R/W
R/W
R/W
R/W
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
MAC_RESET 0
ITXA
PDN:
AUI_TP:
LNK_DIS:
LPBK:
UTP_STP
EXINT
Mnemonic
0
0
0
Reset
MAC software reset
0
1
Insert transmit source address
When set, forces the MAC to automatically insert the
Ethernet source MAC address into the Ethernet transmit
packet. The MAC address information is provided by the
data configured in the Station Address registers (SA1, SA2,
SA3).
When ITXA is cleared, the 7
Ethernet packet are ignored and replaced by the size bytes
in the MAC Address register.
ENDEC media control bits
Used only when the MODE field is configured for ENDEC
mode. In this configuration, each register bit is mapped to
NS7520 pins, allowing the software to manipulate control
signals on an external ENDEC PHY device.
See Table 54 on page 163 for more information.
External interface mode
00
01
10
11
Description
Restore MAC to normal operation
Reset MAC host interface
MII normal operation, used for all MII-style 10/100
PHY devices
TP-PMD mode, used for PHYs that contain their
own non-standard PCS circuitry
10 Mbit mode, used for older
10-Mbit-only PHY devices that predate the MII
standard.
Reserved
th
through 12
th
bytes in the