MT41J256M4JP-125:G Micron Technology Inc, MT41J256M4JP-125:G Datasheet - Page 149

• Manufacturer Part Number: MT41J256M4JP-125:G
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT41J256M4JP-125:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 800MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 97: Self Refresh Entry/Exit Timing
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
Command
RESET# 2
Address
ODT 2
CK#
CKE
CK
NOP
T0
t RP 8
Enter self refresh mode
Notes:
(synchronous)
SRE (REF) 3
t IS
t IS
T1
t CPDED
page 149). Before a command requiring a locked DLL can be applied, a ZQCL command
must be issued,
be off during
1. The clock must be valid and stable meeting
2. ODT must be disabled and R
3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the
5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6.
7.
8. The device must be in the all banks idle state prior to entering self refresh mode. For exam-
9. Self refresh exit is asynchronous; however,
self refresh mode, and at least
stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged
from entry and during self refresh mode, then
t
and R
inputs becoming “Don’t Care.”
t
t
ple, all banks must be precharged,
clock edge where CKE HIGH satisfies
t
CKESR must be satisfied prior to exiting at SRX.
XS is required before any commands not requiring a locked DLL.
XSDLL is required before any commands requiring a locked DLL.
ISXR is satisfied at Tc1.
t CKSRE 1
NOP 4
T2
TT
_
WR
t
XSDLL.
are disabled in the mode registers, ODT can be a “Don’t Care.”
Ta0
t
ZQ
OPER
t CKESR (MIN) 1
timing must be met, and
149
TT
Tb0
off prior to entering self refresh at state T1. If both R
t
CKSRX prior to exiting self refresh mode, if the clock is
t
RP must be met, and no data bursts can be in progress.
t
ISXR at Tc1.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CKSRX 1
Tc0
t IH
t
XS and
t
CK specifications at least
Exit self refresh mode
t
SRX (NOP)
CKSRE and
(asynchronous)
t IS
1Gb: x4, x8, x16 DDR3 SDRAM
t
CKSRX timing is also measured so that
t
t
XSDLL must be satisfied. ODT must
XSDLL timings start at the first rising
Tc1
t
CKSRX do not apply; however,
NOP 5
Td0
©2006 Micron Technology, Inc. All rights reserved.
Indicates A Break in
Time Scale
t
CKSRE after entering
Valid 6
Valid
Valid
Te0
Operations
Valid 7
Valid
Valid
Don’t Care
Valid
Tf0
TT
_
NOM