MT41J256M4JP-125:G Micron Technology Inc, MT41J256M4JP-125:G Datasheet - Page 96

• Manufacturer Part Number: MT41J256M4JP-125:G
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT41J256M4JP-125:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 800MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SELF REFRESH
DLL Disable Mode
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is
2. Enter self refresh mode after
3. After
4. Self refresh may be exited when the clock is stable with the new frequency for
5. The DRAM will be ready for its next command in the DLL disable mode after the
The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in the self refresh mode, the DRAM retains data without
external clocking. The self refresh mode is also a convenient method used to enable/
disable the DLL (see “DLL Disable Mode” on page 96) as well as to change the clock
frequency within the allowed synchronous operating range (see “Input Clock Frequency
Change” on page 99). All power supply inputs (including V
maintained at valid levels upon entry/exit and during SELF REFRESH operation.
If the DLL is disabled by the mode register (MR1[0] can be switched during initialization
or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal
mode with a few notable exceptions:
• The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS
• DLL disable mode affects the read data clock-to-data strobe relationship (
• In normal operation (DLL on),
The ODT feature is not supported during DLL disable mode (including dynamic ODT).
The ODT resistors must be disabled by continuously registering the ODT ball LOW by
programming R
disable mode.
Specific steps must be followed to switch between the DLL enable and DLL disable
modes due to a gap in the allowed clock rates between the two modes (
and
clock rate gap is during self refresh mode. Thus, the required procedure for switching
from the DLL enable mode to the DLL disable mode is to change frequency during self
refresh (see Figure 44 on page 97):
WRITE latency (CWL = 6).
but not the read data-to-data strobe relationship (
needed to line the read data up with the controller time domain when the DLL is
disabled.
cycles after the READ command. In DLL disable mode,
cycles after the READ command. Additionally, with the DLL disabled, the value of
t
turned off, and R
DLL.
After
greater of
appropriate timings met as well.
DQSCK could be larger than
t
CK [DLL disable] MIN, respectively). The only time the clock is allowed to cross this
t
t
CKSRE is satisfied, change the frequency to the desired clock rate.
XS is satisfied, update the mode registers with appropriate values.
t
MRD or
TT
_
NOM
TT
t
_
MOD has been satisfied. A ZQCL command should be issued with
NOM
MR1[9, 6, 2] and R
and R
96
t
t
MOD has been satisfied.
CK.
t
TT
DQSCK starts from the rising clock edge AL + CL
_
WR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
are High-Z), set MR1[0] to “1” to disable the
TT
_
WR
1Gb: x4, x8, x16 DDR3 SDRAM
MR2[10, 9] to “0” while in the DLL
t
DQSQ,
t
REF
DQSCK starts AL + CL - 1
t
CA and V
QH). Special attention is
©2006 Micron Technology, Inc. All rights reserved.
REF
t
CK [AVG] MAX
Commands
DQ) must be
t
DQSCK),
t
CKSRX.