ISP1563BMGE ST-Ericsson Inc, ISP1563BMGE Datasheet - Page 22

• Manufacturer Part Number: ISP1563BMGE
• Description: IC USB PCI HOST CTRLR 128-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGE

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3158; ISP1563BM

Philips Semiconductors
Table 15:
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Header Type register (address 0Eh) bit allocation
8.2.1.10 Base Address register 0
8.2.1.8 Latency Timer register
8.2.1.9 Header Type register
MFD
R
7
1
This field must be initialized to logic 0 on activation of RST#.
description of the CacheLine Size register.
Table 13:
Legend: * reset value
This register specifies, in units of PCI bus clocks, the value of the Latency Timer for the
PCI bus master.
Table 14:
Legend: * reset value
The Header Type register identifies the layout of the second part of the predefined header;
beginning at byte 10h in configuration space. It also identifies whether the device contains
multiple functions. For bit allocation, see
Table 16:
Power-up software must build a consistent address map before booting the machine to an
operating system. This means it must determine how much memory is in the system, and
how much address space the I/O controllers in the system require. After determining this
information, power-up software can map the I/O controllers into reasonable locations and
proceed with system boot. To do this mapping in a device-independent manner, the base
registers for this mapping are placed in the predefined header portion of configuration
space.
Bit 0 in all Base Address registers is read-only and used to determine whether the register
maps into memory or I/O space. Base Address registers that map to memory space must
return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in
bit 0.
Bit
7 to 0 CLS[7:0]
Bit
7 to 0 LT[7:0]
Bit
7
6 to 0
Symbol
Symbol
R
6
0
CLS - CacheLine Size register (address 0Ch) bit description
LT - Latency Timer register (address 0Dh) bit description
Header Type register (address 0Eh) bit description
Symbol
MFD
HT[6:0]
Table 14
Access
R/W
Access
R/W
R
5
0
Rev. 01 — 14 July 2005
Description
Multi-Function Device: This bit identifies a multifunction device.
0 — The device has single function.
1 — The device has multiple functions.
Header Type: These bits identify the layout of the part of the
predefined header, beginning at byte 10h in configuration space.
shows the bit description of the Latency Timer register.
Value
00h*
Value
00h*
R
4
0
Description
CacheLine Size: This byte identifies the system
CacheLine size.
Description
Latency Timer: This byte identifies the latency timer.
Table
HT[6:0]
R
3
0
15.
R
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
Table 13
shows the bit
R
1
0
ISP1563
22 of 107
R
0
0