ISP1563BMGE ST-Ericsson Inc, ISP1563BMGE Datasheet - Page 67

• Manufacturer Part Number: ISP1563BMGE
• Description: IC USB PCI HOST CTRLR 128-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGE

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3158; ISP1563BM

Philips Semiconductors
[1]
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
11.2.2 HceInput register
IRQ12A
R/W
7
0
Table 89:
Address: Value read from func0 or func1 of address 10h + 100h
The HceInput register is a 4 B register, and the bit allocation is given in
that is written to ports 60h and 64h is captured in this register, when emulation is enabled.
This register may be directly read or written by accessing it in the Host Controller’s
operational register space. When directly accessed in a memory cycle, reads and writes
of this register have no side effects.
Bit
31 to 9
8
7
6
5
4
3
2
1
0
IRQ1A
R/W
6
0
Symbol
reserved
A20S
IRQ12A
IRQ1A
GA20S
EIRQEN
IRQEN
C_P
EI
EE
HceControl - Host Controller Emulation Control register bit description
GA20S
R/W
5
0
Description
-
A20 State: This bit indicates the current state of Gate A20 on the keyboard
controller. It is used to compare against value written to 60h when GA20S is
active.
IRQ12 Active: This bit indicates that a positive transition on IRQ12 from the
keyboard controller has occurred.
0 — No effect
1 — Sets IRQ12 to logic 0 (inactive).
IRQ1 Active: This bit indicates that a positive transition on IRQ1 from the
keyboard controller has occurred.
0 — No effect
1 — Sets IRQ11 to logic 0 (inactive).
Gate A20 Sequence: This bit is set by the Host Controller when a data
value of D1h is written to I/O port 64h and cleared on a write to I/O port 64h
of any value other than D1h.
External IRQ Enable: When this bit is set to logic 1, IRQ1 and IRQ12 from
the keyboard controller cause an emulation interrupt. This bit is
independent of the setting of the EE bit in this register.
IRQ Enable: When this bit is set, the Host Controller generates IRQ1 or
IRQ12 as long as OUT_FULL (bit 0 in HceStatus) is logic 1. If
AUX_OUT_FULL (bit 5 in HceStatus) is logic 0, then IRQ1 is generated; if it
is logic 1, then IRQ12 is generated.
Character Pending: When this bit is set, an emulation interrupt is
generated when OUT_FULL is set to logic 0.
Emulation Interrupt: This bit shows the emulation interrupt condition.
0 — Legacy emulation enabled
1 — Legacy emulation disabled.
Emulation Enable: When this bit is set to logic 1, the Host Controller is
enabled for legacy emulation. The Host Controller decodes accesses to I/O
registers 60h and 64h and enables interrupts on IRQ1 or IRQ12, or both.
The Host Controller also generates an emulation interrupt at appropriate
times to invoke the emulation software.
Rev. 01 — 14 July 2005
EIRQEN
R/W
4
0
IRQEN
R/W
3
0
C_P
R/W
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
EI
R
1
0
Table
ISP1563
90. I/O data
R/W
67 of 107
EE
0
0