ISP1563BMGE ST-Ericsson Inc, ISP1563BMGE Datasheet - Page 45

• Manufacturer Part Number: ISP1563BMGE
• Description: IC USB PCI HOST CTRLR 128-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGE

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3158; ISP1563BM

Philips Semiconductors
Table 50:
[1]
9397 750 14224
Product data sheet
Address: Value read from func0 or func1 of address 10h + 10h
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
HcInterruptEnable - Host Controller Interrupt Enable register bit allocation
11.1.5 HcInterruptEnable register
reserved
R/W
R/W
R/W
R/W
MIE
31
23
15
0
0
0
7
0
[1]
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control
which events generate a hardware interrupt. A hardware interrupt is requested on the host
bus if the following conditions occur:
Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to
a bit in this register leaves the corresponding bit unchanged. On a read, the current value
of this register is returned. The bit allocation is given in
Table 51:
Bit
31
30
29 to 7
Address: Value read from func0 or func1 of address 10h + 10h
•
•
•
A bit is set in the HcInterruptStatus register.
The corresponding bit in the HcInterruptEnable register is set.
The MIE (Master Interrupt Enable) bit is set.
RHSC
R/W
R/W
R/W
R/W
OC
30
22
14
0
0
0
6
0
HcInterruptEnable - Host Controller Interrupt Enable register bit description
Symbol
MIE
OC
reserved
FNO
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 14 July 2005
Description
Master Interrupt Enable:
0 — Ignore
1 — Enables interrupt generation by events specified in other bits of this
register.
Ownership Change:
0 — Ignore
1 — Enables interrupt generation because of Ownership Change.
-
R/W
R/W
R/W
R/W
UE
28
20
12
0
0
0
4
0
reserved
reserved
[1]
[1]
R/W
R/W
R/W
R/W
RD
27
19
11
0
0
0
3
0
reserved
Table
[1]
R/W
R/W
R/W
R/W
SF
26
18
10
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
50.
WDH
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
ISP1563
R/W
R/W
R/W
R/W
45 of 107
SO
24
16
0
0
8
0
0
0