ISP1563BMGE ST-Ericsson Inc, ISP1563BMGE Datasheet - Page 83

• Manufacturer Part Number: ISP1563BMGE
• Description: IC USB PCI HOST CTRLR 128-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGE

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3158; ISP1563BM

Philips Semiconductors
Table 114: CONFIGFLAG - Configure Flag register bit allocation
Address: Value read from func2 of address 10h + 60h
[1]
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
11.4.7 CONFIGFLAG register
11.4.8 PORTSC registers 1, 2, 3, 4
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 113: ASYNCLISTADDR - Current Asynchronous List Address register bit description
Address: Value read from func2 of address 10h + 38h
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in
Table 115: CONFIGFLAG - Configure Flag register bit description
Address: Value read from func2 of address 10h + 60h
The Port Status and Control (PORTSC) register is in the auxiliary power well. It is only
reset by hardware when the auxiliary power is initially applied or in response to a Host
Controller reset. The initial conditions of a port are:
Bit
31 to 12
11 to 0
Bit
31 to 1
0
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Symbol
reserved
CF
Symbol
LPL[19:0]
reserved
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Description
-
Configure Flag: The host software sets this bit as the last action in its
process of configuring the Host Controller. This bit controls the default
port-routing control logic.
0 — Port routing control logic default-routes each port to an implementation
dependent classic Host Controller
1 — Port routing control logic default-routes all ports to this Host Controller.
Description
Link Pointer List: These bits correspond to memory address signals
31 to 12, respectively. This field may only reference a Queue Head (QH).
-
Rev. 01 — 14 July 2005
reserved
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
[1]
[1]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
ISP1563
Table
114.
R/W
R/W
R/W
R/W
83 of 107
CF
24
16
0
0
8
0
0
0