AD8112-EVALZ Analog Devices Inc, AD8112-EVALZ Datasheet

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AD8112-EVALZ

Manufacturer Part Number
AD8112-EVALZ
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8112-EVALZ

Lead Free Status / Rohs Status
Compliant
FEATURES
Low cost, 16 × 8, high speed, nonblocking switch array
Serial or parallel programming of switch array
Serial data out allows daisy chaining control of multiple
Output disable allows connection of multiple devices
Complete solution
Excellent audio performance V
Excellent video performance V
Excellent ac performance
Low all-hostile crosstalk of −83 dB at 20 kHz
Reset pin allows disabling of all outputs (connected to a
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
CCTV surveillance/DVR
Analog/digital audio routers
Video routers (NTSC, PAL, S-Video, SECAM)
Multimedia systems
Video conferencing
GENERAL DESCRIPTION
The AD8112 is a low cost, fully buffered crosspoint switch matrix
that operates on ±12 V for audio applications and ±5 V for
video applications. It offers a −3 dB signal bandwidth greater
than 60 MHz and channel switch times of less than 60 ns with
0.1% settling for use in both analog and digital audio. The
AD8112 operated at 20 kHz has a crosstalk performance of
−83 dB and isolation of 90 dB. In addition, ground/power pins
surround all inputs and outputs to provide extra shielding for
operation in the most demanding audio routing applications.
With a differential gain and differential phase better than 0.1%
and 0.1°, respectively, and a 0.1 dB flatness output of up to 10 MHz,
the AD8112 is suitable for many video applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
16 × 8 arrays to create larger switch arrays
without loading the output bus
±10 V output swing
0.002% THD at 20 kHz maximum 20 V p-p (R
0.1 dB gain flatness of 10 MHz
0.1% differential gain error (R
0.1° differential phase error (R
capacitor to ground provides power-on reset capability)
Pin-compatible 16 × 16 version available (AD8113)
Buffered inputs
8 output amplifiers
Operates on ±5 V or ±12 V supplies
Low supply current of 54 mA
−3 dB bandwidth 60 MHz
S
S
= ±5 V
= ±12 V
L
L
= 1 kΩ)
= 1 kΩ)
L
= 600 Ω)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
The AD8112 includes eight independent output buffers that can
be placed into a disabled state for paralleling crosspoint outputs
so that off channel loading is minimized. The AD8112 has a gain
of +2. It operates on voltage supplies of ±5 V or ±12 V while
consuming only 34 mA or 31 mA of current, respectively. The
channel switching is performed via a serial digital control (which
can accommodate the daisy chaining of several devices) or via
a parallel control, allowing updating of an individual output
without reprogramming the entire array.
The AD8112 is packaged in a 100-lead LQFP and is available
over the commercial temperature range of 0°C to 70°C.
Gain of +2 Crosspoint Switch
Audio/Video, 60 MHz, 16 × 8,
UPDATE
DATA IN
RESET
CLK
CE
FUNCTIONAL BLOCK DIAGRAM
AD8112
SER/PAR
8 × 5:16 DECODERS
©2007 Analog Devices, Inc. All rights reserved.
PARALLEL LATCH
80-BIT SHIFT REGISTER
PARALLEL LOADING
D0 D1 D2 D3 D4
DECODE
SWITCH
MATRIX
Figure 1.
WITH 5-BIT
40
40
128
OUTPUT
BUFFER
G = +2
CONNECT
NO
8
40
AD8112
www.analog.com
A0
A1
A2
DATA
OUT

AD8112-EVALZ Summary of contents

Page 1

... L The AD8112 includes eight independent output buffers that can be placed into a disabled state for paralleling crosspoint outputs so that off channel loading is minimized. The AD8112 has a gain of +2. It operates on voltage supplies of ± ±12 V while consuming only current, respectively. The channel switching is performed via a serial digital control (which ...

Page 2

... AD8112 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics (Serial) .................................................. 5 Timing Characteristics (Parallel) ............................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Power Dissipation......................................................................... 7 Pin Configuration and Function Descriptions............................. 9 I/O Schematics............................................................................ 11 Typical Performance Characteristics ........................................... 12 Theory of Operation ...................................................................... 17 REVISION HISTORY 2/07—Revision 0: Initial Version Calculation of Power Dissipation ...

Page 3

... AD8112 Unit MHz MHz MHz MHz MHz ns ns V/μs V/μs % Degrees % nV/√Hz nV/√ ppm/°C Ω kΩ μ ...

Page 4

... AD8112 Parameter SWITCHING CHARACTERISTICS Enable On Time Switching Time Step Switching Transient (Glitch) POWER SUPPLIES Supply Current DYNAMIC PERFORMANCE Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θ JA Conditions 50% update to 1% settling AV outputs enabled, no load ± outputs disabled ± outputs enabled, no load ± ...

Page 5

... IH 20 μA max 2.7 V min 0.5 V max Rev Page Limit Min Typ Max 20 1 100 100 200 100 200 OUT00 (D0 TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL −400 μA min −400 μA max AD8112 Unit μ 3.0 mA min ...

Page 6

... AD8112 TIMING CHARACTERISTICS (PARALLEL) Table 4. Parameter Data Setup Time CLK Pulse Width Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and Fall Times RESET Time 1 CLK LATCHED UPDATE 0 = TRANSPARENT Table 5 ...

Page 7

... ESD CAUTION POWER DISSIPATION The AD8112 is operated with ± ±12 V supplies and can Rating drive loads down to 150 Ω (± 600 Ω (±12 V), resulting 26 large range of possible power dissipations. For this reason, ...

Page 8

... AD8112 Table 7. Operation Truth Table CE UPDATE CLK DATA IN DATA OUT Data Data ... D4, N ... A2 Parallel Mode PARALLEL D1 DATA D2 D3 (OUTPUT D4 ENABLE) SER/PAR DATA (SERIAL) CLK CLK CLK CE UPDATE OUT00 EN OUT01 EN OUT02 EN OUT03 EN A0 OUT04 EN OUT05 EN A1 OUT06 EN A2 OUT07 OUT00 OUT00 B0 B1 ...

Page 9

... Analog Outputs for Channel Numbers 00 Through 07. OUT00 to 1 OUT07 AGND Analog Ground for Inputs and Switch Matrix. Must be connected for Digital Circuitry. CC DGND Ground for Digital Circuitry. AV −5 V for Inputs and Switch Matrix. EE Rev Page AD8112 DGND 74 AGND 73 IN07 72 71 AGND IN06 70 69 ...

Page 10

... AD8112 Pin No. 21, 22, 26, 30, 34, 38 50, 46, 42 52, 48, 44 23, 25, 27, 29, 31, 33, 35, 37 Chanel numbers 00 through 15 for analog inputs channel numbers 00 through 07 for analog outputs. Mnemonic Description for Inputs and Switch Matrix for Output Amplifier. This pin is shared by Channel Numbers xx and yy. ...

Page 11

... Figure 7. Analog Input V CC ESD ESD AV EE Figure 8. Analog Output V CC ESD 20kΩ RESET ESD DGND Figure 9. Reset Input OUTPUT Rev Page AD8112 V CC ESD INPUT ESD DGND Figure 10. Logic Input V CC 2kΩ ESD OUTPUT ESD DGND Figure 11. Logic Output ...

Page 12

... AD8112 TYPICAL PERFORMANCE CHARACTERISTICS 3 0 –3 –6 0.01 0.1 1 FREQUENCY (MHz) Figure 12. Small-Signal Bandwidth ± 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 0.1 1 FREQUENCY (MHz) Figure 13. Small-Signal Gain Flatness ± –3 –6 0.1 1 FREQUENCY (MHz) Figure 14. Large-Signal Bandwidth ± 100 = 150 Ω 200 mV p-p Figure 15 ...

Page 13

... ALL HOSTILE –50 –60 ADJACENT –70 –80 –90 0.01 0 FREQUENCY (MHz) = ± 600 Ω –70 –75 –80 –85 SECOND HARMONIC –90 –95 THIRD HARMONIC 0.001 0.01 0.1 FREQUENCY (MHz) = ± 600 Ω AD8112 p-p OUT 100 = 20 V p-p OUT p-p OUT ...

Page 14

... AD8112 300 250 200 V = ±12V 150 600Ω L 100 SERIES RESISTANCE (Ω) Figure 24. Capacitive Load vs. Series Resistance for Less than 30% Overshoot 10k 1k 100 FREQUENCY (MHz) Figure 25. Disabled Output Impedance vs. Frequency 100 10 1 0.1 0 FREQUENCY (MHz) Figure 26. Enabled Output Impedance vs. Frequency ± ...

Page 15

... Figure 35. Small-Signal Pulse Response Rev Page +PSRR –PSRR 0.01 0.1 1 FREQUENCY (MHz) Figure 33. PSRR vs. Frequency ± ±12V 600Ω p-p OUT V = ± 150Ω OUT 0 FREQUENCY (MHz) Figure 34. Off Isolation vs. Frequency 100ns/DIV = ± AD8112 p-p 100 = 600 Ω L ...

Page 16

... AD8112 500mV/DIV 100ns/DIV Figure 36. Large-Signal Pulse Response, V UPDATE 2V/DIV V OUT INPUT 0 100ns/DIV Figure 37. Switching Time ± UPDATE 1V/DIV OUTPUT 20mV/DIV 100ns/DIV Figure 38. Switching Transient ± 5V/DIV = ± 150 Ω Figure 39. Large-Signal Pulse Response 2V/DIV INPUT 1 10V/DIV = 150 Ω L 1V/DIV 20mV/DIV = 150 Ω ...

Page 17

... THEORY OF OPERATION The AD8112 has a gain of +2 and is a crosspoint array with eight outputs, each of which can be connected to any one of 16 inputs. Organized by output row, 16 switchable transconductance stages are connected to each output buffer in the form of a 16-to-1 multiplexer. Each of the 16 rows of transconductance stages are wired in parallel to the 16 input pins, for a total array of 256 trans- conductance stages ...

Page 18

... AD8112 When calculating on-chip power dissipation necessary to include the rms current being delivered to the load multiplied by the rms voltage drop on the AD8112 output devices. The dissipation of the on-chip, 4 kΩ feedback resistor network must also be included. For a sinusoidal output, the on-chip ...

Page 19

... One important consideration when using parallel programming is that the RESET signal does not reset all registers in the AD8112. When taken low, the RESET signal only sets each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs will not be active at the same time ...

Page 20

... CREATING UNITY-GAIN CHANNELS The channels in the AD8112 each have a gain of +2. This gain is necessary, as opposed to a gain of unity, to restrict the voltage on internal nodes to less than the breakdown voltage desired to create channels with an overall gain of unity, a resistive divider can be used at the input to divide the signals by 2 ...

Page 21

... Video signals usually use 75 Ω transmission lines that need to be terminated with this value of resistance at each end. When such a source is delivered to one of the AD8112 inputs, the high input impedance does not properly terminate these signals. Therefore, the line should be terminated with a 75 Ω shunt resistor to ground ...

Page 22

... R TERM IN64 TO IN79 1kΩ TERM IN80 TO IN95 1kΩ TERM IN96 TO IN111 1kΩ TERM IN112 TO IN127 1kΩ TERM RANK 1 (8 × AD8112) 128:16 1kΩ 4 AD8112 1kΩ 4 1kΩ 4 AD8112 1kΩ 4 1kΩ 4 AD8112 1kΩ 4 16:8 NONBLOCKING (16:16 BLOCKING) 1kΩ AD8112 1kΩ ...

Page 23

... When there are many signals in close proximity in a system, as undoubtedly is the case in a system that uses the AD8112, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more AD8112s ...

Page 24

... Areas of Crosstalk A practical AD8112 circuit must be mounted to some sort of circuit board to connect it to power supplies and measurement equipment. Great care has been taken to create a characteriza- tion board (also available as an evaluation board) that adds minimum crosstalk to the intrinsic device ...

Page 25

... On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8112 is specified with excellent differential gain and phase when driving a standard 150 Ω video load, the crosstalk is higher than the minimum obtainable crosstalk due to the high output currents ...

Page 26

... The areas that must be carefully designed are grounding, shielding, signal routing, and supply bypassing. The packaging of the AD8112 is designed to help minimize crosstalk. Each input is separated from each other input by an analog ground pin. All of these AGNDs should be directly connected to the ground plane of the circuit board ...

Page 27

... C = OPTIONAL SMOOTHING CAPACITOR CONNECT 0.01µF 0.01µF 0.01µ 21 AD8112 Figure 48. Evaluation Board Schematic Rev Page AD8112 OUTPUT 00 0.01µF 75Ω 53 OUT00 00/01 OUTPUT 01 0.01µF 75Ω 51 OUT01 01/02 OUTPUT 02 0.01µF 75Ω 49 OUT02 02/03 OUTPUT 02 0.01µF 75Ω 47 OUT03 ...

Page 28

... PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD8112JSTZ 1 0°C to 70°C 1 AD8112-EVALZ Pb-free part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 1.60 MAX 0.75 100 1 0.60 0.45 PIN 1 0 ...