AD8112-EVALZ Analog Devices Inc, AD8112-EVALZ Datasheet - Page 17

• Manufacturer Part Number: AD8112-EVALZ
• Manufacturer: Analog Devices Inc

Specifications of AD8112-EVALZ

• Lead Free Status / Rohs Status: Compliant

THEORY OF OPERATION
The AD8112 has a gain of +2 and is a crosspoint array with
eight outputs, each of which can be connected to any one of 16
inputs. Organized by output row, 16 switchable transconductance
stages are connected to each output buffer in the form of a 16-to-1
multiplexer. Each of the 16 rows of transconductance stages are
wired in parallel to the 16 input pins, for a total array of 256 trans-
conductance stages. Decoding logic for each output selects one
(or none) of the transconductance stages to drive the output
stage. The transconductance stages are NPN input differential
pairs, sourcing current into the folded cascode output stage.
The compensation networks and emitter follower output buffers
are in the output stage. Voltage feedback sets the gain at +2.
When operated with ±12 V supplies, this architecture provides
±10 V drive for 600 Ω audio loads with extremely low distortion
(<0.002%) at audio frequencies. Provided the supplies are low-
ered to ±5 V (to limit power consumption), the AD8112 can
drive reverse-terminated video loads, swinging ±3.0 V into
150 Ω. Disabling unused outputs and transconductance
stages minimizes on-chip power consumption.
Features of the AD8112 facilitate the construction of larger
switch matrices. The unused outputs can be disabled, leaving
only a feedback network resistance of 4 kΩ on the output. This
allows multiple ICs to be bused together, provided the output
load impedance is greater than the minimum allowed values.
Because no additional input buffering is necessary, high input
resistance and low input capacitance are easily achieved without
additional signal degradation.
The AD8112 inputs have a unique bias current compensation
scheme that overcomes a problem common to transconductance
input array architectures. Typically, an input bias current increases
as more transconductance stages connected to the same input
are turned on. Anywhere from zero to 16 transconductance
stages can share one input pin, so there is a varying amount of
bias current supplied through the source impedance driving
the input. For audio systems with larger source impedances,
this has the potential of creating large offset voltages, audible
as pops when switching between channels. The AD8112 samples
and cancels the input bias current contributions from each
transconductance stage so that the residual bias current is
nominally zero regardless of the number of enabled inputs.
Due to the flexibility in allowed supply voltages, internal cross-
talk isolation clamps have variable bias levels. These levels were
chosen to allow for the necessary input range to accommodate
the full output swing with a gain of +2. Overdriving the inputs
beyond the device’s linear range will eventually forward bias
Rev. 0 | Page 17 of 28
these clamps, increasing power dissipation. The valid input
range for ±12 V supplies is ±5 V. The valid input range for ±5 V
supplies is ±1.5 V. When outputs are disabled and being driven
externally, the voltage applied to them should not exceed the
valid output swing range for the AD8112. Exceeding ±10.5 V on
the outputs of the AD8112 may apply a large differential voltage
on the unused transconductance stages and should be avoided.
A flexible TTL-compatible logic interface simplifies the pro-
gramming of the matrix. Either parallel or serial loading into
a first rank of latches programs each output. A global latch
simultaneously updates all outputs. In serial mode, a serial
output pin allows devices to be daisy-chained together for
single pin programming of multiple ICs. A power-on reset
pin is available to avoid bus conflicts by disabling all outputs.
Regardless of the supply voltage applied to the AV
pins, the digital logic requires 5 V on the DV
to DGND. In order for the digital-to-analog interface to work
properly, DV
ESD protection diodes require that the DGND and AGND pins
be at the same potential.
CALCULATION OF POWER DISSIPATION
The curve in Figure 42 was calculated from
As an example, if the AD8112 is enclosed in an environment
at 50°C (T
supply conditions must not be allowed to exceed 2.5 W.
Figure 42. Maximum Power Dissipation vs. Ambient Temperature
P
D
,
4.0
3.5
3.0
2.5
2.0
MAX
A
0
), the total on-chip dissipation under all load and
=
CC
(
T
must be at least 7 V above AV
10
JUNCTION
AMBIENT TEMPERATURE (°C)
20
,
MAX
θ
JA
−
30
T
AMBIENT
40
)
50
CC
EE
T
. Finally, internal
pin with respect
J
= 150°C
60
CC
AD8112
and AV
70
EE