AD8112-EVALZ Analog Devices Inc, AD8112-EVALZ Datasheet - Page 9

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AD8112-EVALZ

Manufacturer Part Number
AD8112-EVALZ
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8112-EVALZ

Lead Free Status / Rohs Status
Compliant
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
58, 60, 62, 64, 66, 68, 70, 72, 4, 6, 8, 10,
12, 14, 16, 18
96
97
98
95
100
99
94
53, 51, 49, 47, 45, 43, 41, 39
3, 5, 7, 9, 11, 13, 15, 17, 19, 57, 59, 61, 63,
65, 67, 69, 71, 73
1, 75
2, 74, 81
20, 24, 28, 32, 36, 56
NC = NO CONNECT
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DV
AV
AV
AV
AV
IN08
IN09
IN10
IN11
IN12
IN13
IN14
IN15
NC
NC
CC
CC
CC
EE
EE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
6
5
7
8
9
PIN 1
Mnemonic
IN00 to IN15
DATA IN
CLK
DATA OUT
UPDATE
RESET
CE
SER/PAR
OUT00 to
OUT07
AGND
DV
DGND
AV
EE
CC
1
1
Figure 6. Pin Configuration
Description
Analog Inputs for Channel Numbers 00 through 15.
Serial Data Input, TTL-compatible.
Clock, TTL-compatible. Falling edge triggered.
Serial Data Output, TTL-compatible.
Enable (Transparent) Low. Allows serial register to connect directly to switch
matrix. Data latched when high.
Disable Outputs, Active Low.
Chip Enable, Enable Low. Must be low to clock in and latch data.
Serial Data/Parallel Data. When low, this pin selects serial data mode; when
high, this pin selects parallel data mode, high. Must be connected.
Analog Outputs for Channel Numbers 00 Through 07.
Analog Ground for Inputs and Switch Matrix. Must be connected.
5 V for Digital Circuitry.
Ground for Digital Circuitry.
−5 V for Inputs and Switch Matrix.
Rev. 0 | Page 9 of 28
(Not to Scale)
AD8112
TOP VIEW
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DV
DGND
AGND
IN07
AGND
IN06
AGND
IN05
AGND
IN04
AGND
IN03
AGND
IN02
AGND
IN01
AGND
IN00
AGND
AV
AV
AV
OUT00
AV
OUT01
CC
EE
CC
CC
EE
00/01
00
AD8112