AD8112-EVALZ Analog Devices Inc, AD8112-EVALZ Datasheet - Page 8

• Manufacturer Part Number: AD8112-EVALZ
• Manufacturer: Analog Devices Inc

Specifications of AD8112-EVALZ

• Lead Free Status / Rohs Status: Compliant

AD8112
Table 7. Operation Truth Table
CE
1
0
0
0
X
PARALLEL
UPDATE
A0
A1
A2
(OUTPUT ENABLE)
(OUTPUT
ENABLE)
SER/PAR
(SERIAL)
DATA IN
DATA
CLK
CE
UPDATE
X
1
1
0
X
OUT00 EN
OUT01 EN
OUT02 EN
OUT03 EN
OUT04 EN
OUT05 EN
OUT06 EN
OUT07 EN
RESET
D0
D1
D2
D3
D4
CLK
X
X
X
D1
D0
S
Q
CLK
D
OUT00
LE
Q
B0
DATA IN
X
Data
D0 ... D4,
A0 ... A2
X
X
D
Q
D1
D0
S
Q
i
D
CLK
OUT00
LE
Q
B1
Q
D
D1
D0
S
X
DATA OUT
Data
N/A in
Parallel
Mode
X
X
Q
D Q
CLK
OUT00
LE
B2
i-80
Q
D
D1
D0
S
Q
D Q
CLK
OUT00
LE
B3
RESET
X
1
1
1
0
D
Q
D1
D0
SWITCH MATRIX
S
Q
D Q
CLK
CLR
OUT00
LE
EN
Figure 5. Logic Diagram
D
Q
Rev. 0 | Page 8 of 28
SER/PAR
X
0
1
X
X
128
D1
D0
S
Q
D Q
CLK
OUT01
LE
B0
Q
D
DECODE
Operation/Comment
No change in logic.
The data on the serial DATA IN line is loaded into serial register.
The first bit clocked into the serial register appears at DATA OUT
80 clocks later.
The data on the parallel data lines, D0 to D4, is loaded into the
80-bit serial shift register location addressed by A0 to A2.
Data in the 80-bit shift register transfers into the parallel
latches that control the switch array. Latches are transparent.
Asynchronous operation. All outputs are disabled. Remainder
of logic is unchanged.
D1
D0
S
Q
D Q
CLK
CLR
OUT06
LE
EN
D
Q
D1
D0
S
Q
D Q
CLK
OUT07
LE
B0
Q
D
D1
D0
S
Q
D Q
CLK
OUT07
LE
B1
Q
D
D1
D0
OUTPUT ENABLE
S
Q
D Q
CLK
OUT07
LE
B2
Q
D
8
D1
D0
S
Q
D Q
CLK
OUT07
LE
B3
D
Q
D1
D0
S
Q
D Q
CLK
CLR
OUT07
LE
EN
D
Q
DATA OUT