AD8112-EVALZ Analog Devices Inc, AD8112-EVALZ Datasheet - Page 5

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AD8112-EVALZ

Manufacturer Part Number
AD8112-EVALZ
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8112-EVALZ

Lead Free Status / Rohs Status
Compliant
TIMING CHARACTERISTICS (SERIAL)
Table 2.
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid, Serial Mode
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
RESET Time
Table 3. Logic Levels
Pins
RESET, SER/PAR,
CLK, DATA IN, CE,
UPDATE
DATA OUT
0 = TRANSPARENT
1 = LATCHED
V
2.0 V min
IH
DATA OUT
UPDATE
DATA IN
CLK
1
0
1
0
V
0.8 V max
IL
OUT07 (D4)
t
1
t
t
3
7
t
2
V
2.7 V min
OH
Figure 2. Timing Diagram, Serial Mode
t
4
Rev. 0 | Page 5 of 28
V
0.5 V max
OUT07 (D3)
OL
ON FALLING EDGE
SERIAL REGISTER
LOAD DATA INTO
I
20 μA max
IH
Symbol
t
t
t
t
t
t
t
1
2
3
4
5
6
7
TRANSFER DATA FROM SERIAL
LATCHES DURING LOW LEVEL
REGISTER TO PARALLEL
I
−400 μA min
IL
Min
20
100
20
100
0
50
t
5
OUT00 (D0)
Typ
16
I
−400 μA max
Limit
OH
t
6
Max
200
50
100
200
I
3.0 mA min
AD8112
OL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns