P89C51RB2HBA NXP Semiconductors, P89C51RB2HBA Datasheet - Page 19

• Manufacturer Part Number: P89C51RB2HBA
• Manufacturer: NXP Semiconductors

Specifications of P89C51RB2HBA

• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 33MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 512Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Philips Semiconductors
2002 May 24
NOTE:
*SMOD0 is located at PCON6.
**f
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
OSC
Tl
Symbol
FE
SM0
SM1
SM2
REN
TB8
RB8
Rl
= oscillator frequency
Bit Addressable
Bit:
Function
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
0
0
1
1
SCON Address = 98H
(SMOD0 = 0/1)*
SM0/FE
7
SM1
0
1
0
1
SM1
Mode
6
0
1
2
3
Figure 7. SCON: Serial Port Control Register
SM2
5
Description
shift register
8-bit UART
9-bit UART
9-bit UART
REN
4
Baud Rate**
f
variable
f
f
variable
OSC
OSC
OSC
16
TB8
/6 (6-clock mode) or f
/32 or f
/64 or f
3
OSC
OSC
RB8
/16 (6-clock mode) or
/32 (12-clock mode)
2
OSC
P89C51RB2/P89C51RC2/
Tl
1
/12 (12-clock mode)
Rl
0
Reset Value = 0000 0000B
P89C51RD2Hxx
SU01255
Product data