P89C51RB2HBA NXP Semiconductors, P89C51RB2HBA Datasheet - Page 33

• Manufacturer Part Number: P89C51RB2HBA
• Manufacturer: NXP Semiconductors

Specifications of P89C51RB2HBA

• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 33MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 512Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Philips Semiconductors
HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR P89C51RB2/RC2/RD2Hxx)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit
counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1H in
sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and
there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an
output reset HIGH pulse at the RST-pin (see the note below).
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to
service it by writing 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this
will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset
the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only
register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the reset pin (see note
below). The RESET pulse duration is 98 T
should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.
2002 May 24
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
100
256 or 768 BYTES
Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0
ERAM
OSC
(6 clock mode; 196 in 12 clock mode), where T
FF
80
00
INTERNAL RAM
INTERNAL RAM
128 BYTES
128 BYTES
LOWER
UPPER
30
FF
80
00
FUNCTION
REGISTER
SPECIAL
OSC
P89C51RB2/P89C51RC2/
= 1/f
FFFF
0000
OSC
. To make the best use of the WDT, it
EXTERNAL
MEMORY
DATA
P89C51RD2Hxx
SU01293
Product data