P89C51RB2HBA NXP Semiconductors, P89C51RB2HBA Datasheet - Page 21

• Manufacturer Part Number: P89C51RB2HBA
• Manufacturer: NXP Semiconductors

Specifications of P89C51RB2HBA

• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 33MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 512Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

1. L = Level activated
2. T = Transition activated
Philips Semiconductors
Interrupt Priority Structure
The P89C51RB2/RC2/RD2Hxx has a 7 source four-level interrupt
structure (see Table 6).
There are 3 SFRs associated with the four-level interrupt. They are
the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt
Priority High) register makes the four-level interrupt structure
possible. The IPH is located at SFR address B7H. The structure of
the IPH register and a description of its bits is shown in Figure 12.
The function of the IPH SFR, when combined with the IP SFR,
determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
Table 6.
NOTES:
2002 May 24
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
IPH.x
PRIORITY BITS
0
0
1
1
SOURCE
BIT
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
PCA
SP
X0
T0
X1
T1
T2
Interrupt Table
IE (0A8H)
IP.x
0
1
0
1
SYMBOL
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
INTERRUPT PRIORITY LEVEL
INTERRUPT PRIORITY LEVEL
POLLING PRIORITY
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
PCA interrupt enable bit
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
EA
7
1
2
3
4
5
6
7
EC
6
ET2
5
Figure 10. IE Registers
REQUEST BITS
ES
4
TF2, EXF2
CF, CCFn
n = 0–4
RI, TI
TP0
TF1
IE0
IE1
18
ET1
as on the 80C51. An interrupt will be serviced as long as an interrupt
3
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.
EX1
2
HARDWARE CLEAR?
N (L)
ET0
N (L) Y (T)
P89C51RB2/P89C51RC2/
1
1
Y
Y
N
N
N
Y (T)
EX0
0
2
P89C51RD2Hxx
VECTOR ADDRESS
SU01290
0BH
1BH
2BH
03H
13H
33H
23H
Product data