LH28F008SAT-12 Sharp Electronics, LH28F008SAT-12 Datasheet
LH28F008SAT-12
Specifications of LH28F008SAT-12
Related parts for LH28F008SAT-12
LH28F008SAT-12 Summary of contents
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... Hardware Data Protection Feature – Erase/Write Lockout during Power Transitions • Independent Software Vendor Support – Microsoft Flash File System™ (FFS) • ETOX™ Nonvolatile Flash Technology – Byte Write/Block Erase • Industry Standard Packaging – 40-Pin 1.2 mm × × TSOP (Type I) Package – ...
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... The LH28F008SA brings new capabilities to portable computing. Application and operating sys- tem software stored in resident flash memory arrays provide instant-on rapid execute-in-place and protec- tion from obsolescence through in-system software updates. Resident software also extends system bat- tery life and increases relaibility by reducing disk drive accesses ...
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... Flash Memory INPUT BUFFER Y-DECODER ADDRESS LATCH X-DECODER ADDRESS COUNTER OUTPUT INPUT BUFFER BUFFER IDENTIFIER REGISTER OUTPUT DATA MULTIPLEXER REGISTER STATUS REGISTER DATA COMPARATOR Y-GATING 16 64KB BLOCKS Figure 3. LH28F008SA Block Diagram LH28F008SA I/O LOGIC CE COMMAND WE USER OE INTERFACE PWD WRITE STATE ...
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... DEVICE POWER SUPPLY ±10 ±5%) CC GND SUPPLY GROUND 4 NAME AND FUNCTION » » is active low: CE high deselects the memory device and » is active low. » » always active and does NOT float < memory contents cannot be altered. PP PPLMAX 8M (1M × 8) Flash Memory / BY » » ...
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... Flash Memory » » The output gives an additional indicator of WSM activity, providing capability for both hardware sig- nal of status (versus software polling) and status mask- ing (interrupt masking for background erase, for example). Status polling using RY ...
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... Applications and Motherboard Solid-State Disk CSL CE 1 CSH OTHER LH28F008SA's PLD RY/BY 1 RY/BY 2 RY/BY FROM OTHER LH28F008SA's PWD PWD TO OTHER LH28F008SA PAIRS » » Masking and Selective Powerdown), for DRAM 8M (1M × 8) Flash Memory SWITCH GPIO RESET 28F008SA-3 ...
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... Interface write sequence provides additional software write protection. BUS OPERATION Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Read The LH28F008SA has three read modes. The ...
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... Write X B0H 2 Write WA 40H 2 Write WA 10H » (1M × 8) Flash Memory » the LH28F008SA is deselected dur- . Current draw through V IL typically 0.1 µA. During read PP PHQV after PWD goes to PHWL ) is required before another command can IH SECOND BUS CYCLE NOTE OPER ...
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... Flash Memory Intelligent Identifier Operation The intelligent identifier operation outputs the manu- facturer code 89H; and the device code, A2H for the LH28F008SA. The system CPU can then automatically match the device with its proper block erase and byte write algorithms ...
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... Polling the WSM Status and Erase Suspend Status bits will determined when the erase operation has been suspended (both will be set to '1'). » » will also transition (1M × 8) Flash Memory Status bit (SR.3) MUST be re PPL PPH ...
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... Flash Memory At this point, a Read Array command can be written to the Command User Interface to read data from blocks other than that which is suspended. The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H), at which time the WSM will continue with the erase process ...
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... V come voltage slumps caused by PC board trace inductances. V Trace on Printed Circuit Boards PP Writing flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the V The V pin supplies the memory cell current for writ- PP ing and erasing ...
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... Flash Memory START WRITE 40H (10H), BYTE ADDRESS WRITE BYTE ADDRESS/DATA WSM NO READY? YES FULL STATUS CHECK IF DESIRED BYTE WRITE COMPLETED FULL STATUS CHECK PROCEDURE STATUS REGISTER DATA READ (see above RANGE SR ERROR ? YES NO BYTE WRITE SR ERROR ? YES BYTE WRITE SUCCESSFUL Figure 5 ...
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... SR.5 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 8M (1M × 8) Flash Memory COMMENTS Data = 20H Addr = Within block to be erased ...
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... Read Array Read Write Erase Resume device operation, but also for data retention during system idle time. Flash nonvolatility increases usable when V is active. PP battery life, because the LH28F008SA does not con- sume any power to retain code or data when the sys- tem is off. In addition, the LH28F008SA’ ...
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... CE = PWD = Vcc ±0.2 V PWD = GND ±0.2 0.20 1.2 µA I OUT 35 MHz, I CMOS Inputs 50 MHz, I TTL Inputs 8M (1M × 8) Flash Memory 2.0 V for periods < 20 ns. CC specifications reference the CC TEST CONDITIONS NOTE MAX GND MAX GND CC OUT CC MAX., CE » = PWD = MAX ...
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... Flash Memory DC Characteristics (Continued) SYMBOL PARAMETER I V Byte Write Current CCW Block Erase Current CCE Erase Suspend Current CCES Standby Current PPS Deep Power Down Current PPD Byte Write Current PPW Block Erase Current PPE Erase Suspend Current PPES ...
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... Input rise Input rise and fall times (10% to 90%) < 28F008SA-8 1 HIGH SPEED AC TESTING LOAD CIRCUIT OUT NOTE Includes Jig Capacitance 3 28F008SA-10 8M (1M × 8) Flash Memory 2 1.5 1.5 OUTPUT TEST POINTS 28F008SA-9 1.3 V 1N914 R L DEVICE UNDER OUT TEST C L 28F008SA-11 2 ...
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... Flash Memory AC CHARACTERISTICS - Read Only Operations SYMBOL PARAMETER t t Read Cycle Time AVAV Address to Output Delay AVQV ACC » Output Delay ELQV PWD High to Output Delay PHQV PWH » Output Delay GLQV OE » Output Low Z ELQX LZ » High to Output High Z ...
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... V CC GND V IH PWD ( Figure 8. AC Waveform for Read Operations 20 DEVICE AND ADDRESS OUTPUTS STANDBY SELECTION ENABLED ADDRESSES STABLE t AVAV t GLQV t ELQV t GLQX t ELQX t AVQV t PHQV 8M (1M × 8) Flash Memory DATA V CC VALID STANDBY POWER-DOWN . . . . . . . . . t EHQZ . . . t GHQZ HIGH-Z VALID OUTPUT . . . 28F008SA-12 ...
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... Refer to Command Definitions Table for valid D 5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). ...
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... ADDRESS AND DATA AUTOMATED (BYTE WRITE) OR BYTE WRITE ERASE CONFIRM OR ERASE COMMAND DELAY AVAV AVWH WHAX t WHGL t WHEH t t WHWL WHQV1 DVWH t WHDX WHRL t VPWH 8M (1M × 8) Flash Memory NOTE READ STATUS WRITE READ REGISTER DATA ARRAY COMMAND VALID D IN SRD t QVVL 28F008SA-13 ...
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... Flash Memory ALTERNATIVE CE » - CONTROLLED WRITES SYMBOL PARAMETER t t Write Cycle Time AVAV WC PWD High Recovery PHEL PS Going Low Setup to CE » Going Low WLEL » CE Pulse Width ELEH » V Setup to CE Going High VPEH VPS PP Address Setup to CE ...
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... ADDRESS AND DATA AUTOMATED (BYTE WRITE) OR BYTE WRITE ERASE CONFIRM OR ERASE COMMAND DELAY AVEH EHAX t EHGL t EHWH t t EHEL EHQV1 DVEH t EHDX EHRL t VPEH 8M (1M × 8) Flash Memory READ STATUS WRITE READ REGISTER DATA ARRAY COMMAND VALID D IN SRD t QVVL 28F008SA-14 ...
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... Flash Memory 44SOP (SOP044-P-0600) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012 28.40 [1.118] 28.00 [1.102] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 23 13.40 [0.528] 16.40 [0.646] 13.00 [0.512] 15.60 [0.614] SEE 22 DETAIL 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2 ...
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... MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH28F008SA X -## Device Type Package Speed Example: LH28F008SAT-85 (8M ( Flash Memory, 85 ns, 40-pin TSOP) 26 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] 20.30 [0.799] 19.70 [0.776 120 Access Time (ns) T 40-pin, 1 TSOP (Type I) (TSOP040-P-1020) ...
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... Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Telex: 49608472 (SHARPCAM) Facsimile: (360) 834-8903 http://www.sharpmeg.com ©1997 by SHARP Corporation Issued July 1994 EUROPE SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstraße 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Telex: 2161867 (HEEG D) Facsimile: (49) 40 2376-2232 LH28F008SA ...