LH28F008SAT-12 Sharp Electronics, LH28F008SAT-12 Datasheet - Page 9

• Manufacturer Part Number: LH28F008SAT-12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SAT-12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

8M (1M × 8) Flash Memory
Intelligent Identifier Operation
facturer code 89H; and the device code, A2H for the
LH28F008SA. The system CPU can then automatically
match the device with its proper block erase and byte
write algorithms.
Command User Interface. Following a write of 90H to
the Command User Interface, a read from address
location 00000H outputs the manufacturer code (89H).
A read from address 00001H outputs the device code
(A2H). It is not necessary to have high voltage applied
to V
mand User Interface.
Write
ing of device data and intelligent identifiers. They also
control inspection and clearing of the Status Register.
Additionally, when V
Interface controls block erasure and byte write. The con-
tents of the interface register serve as input to the inter-
nal state machine.
an addressable memory location. The interface register
is a latch used to store the command and address and
Status Register Definitions
The intelligent identifier operation outputs the manu-
The manufacturer and device-codes are read via the
Writes to the Command User Interface enable read-
The Command User Interface itself does not occupy
SR.7
SR.6
SR.5
SR.4
SR.3
PP
WSMS
7
to read the intelligent identifiers from the Com-
= WRITE STATE MACHINE STATUS (WSMS)
= ERASE-SUSPEND STATUS (ESS)
= ERASE STATUS (ES)
= BYTE WRITE STATUS (BWS)
= V
1 = Ready
0 = Busy
1 = Erase Suspended
0 = Erase in Progress/Completed
1 = Error in Block Erasure
0 = Successful Block Erase
1 = Error in Byte Write
0 = Successful Byte Write
1 = V
0 = V
PP
STATUS (VPPS)
PP
PP
Low Detect, Operation Abort
OK
ESS
6
PP
= V
PPH
, the Command User
ES
5
BWS
4
data information needed to execute the command. Erase
Setup and Erase Confirm commands require both
appropriate command data and an address within the
block to be erased. The Byte Write Setup command
requires both appropriate command data and the ad-
dress of the location to be written, while the Byte Write
command consists of the data to be written and the
address of the location to be written.
WE
and data are latched on the rising edge of WE
dard microprocessor write timings are used.
forms for Write Operations, Figure 9, for specific timing
parameters.
COMMAND DEFINITIONS
from the Status Register, intelligent identifiers, or array
blocks are enabled. Placing V
cessful byte write and block erase operations as well.
commands into the Command User Interface. Command
Definitions Table defines the LH28F008SA commands.
NOTES:
1. RY
2. If the Byte Write AND Erase Status bits are set to '1's
3. If V
4. SR.2 - SR.0 = Reserved for future enhancements.
VPPS
The Command User Interface is written by bringing
Refer to AC Write Characteristics and the AC Wave-
When V
Device operations are selected by writing specific
checked to determine byte write or block erase operation,
before the Byte Write or Erase Status bit are checked to
success.
during a block erase attempt, an improper command se-
quence was entered. Attempt the operation again.
cleared before another byte write or block erase operation
is attempted. The V
does not provide continuous indication of V
WSM interrogates the V
block erase command sequences have been entered and
informs the system if V
V
back between V
These bits are reserved for future use and should be
masked out when polling the Status Register.
»
3
PP
to a logic-low level (V
»
/ BY
PP
Status bit is not gauranteed to report accurate feed-
low status is detected, the Status Register must be
»
or the Write State Machine Status bit must first be
PPL
is applied to the V
PPL
R
2
PP
and V
Status bit, unlike an A/D converter,
PP
PP
PPH
has not been switched on. The
level only after the byte write or
IL
) while CE
.
PPH
PP
R
1
on V
pin, read operations
»
is low. Addresses
PP
PP
LH28F008SA
level. The
enables suc-
R
0
»
. Stan-
9