LH28F008SAT-12 Sharp Electronics, LH28F008SAT-12 Datasheet - Page 12

• Manufacturer Part Number: LH28F008SAT-12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SAT-12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

LH28F008SA
DESIGN CONSIDERATIONS
Three-Line Output Control
arrays. Intel provides three control inputs to accommo-
date multiple memory connections. Three-line control
provides for:
•
•
coder should enable CE
to all memory devices and the system’s READ control
line. This assures that only selected memory devices
have active outputs while deselected memory devices
are in Standby Mode. Finally, PWD should either be tied
to the system RESET, or connected to V
NOTE:
1. Assumptions: 10K file written every 10 minutes.
RY
ware method of detecting byte write and block erase
completion. It transitions low time t
erase command sequence is written to the
LH28F008SA, and returns to V
finished executing the internal algorithm.
system CPU or controller. It is active at all times, not
instated if the LH28F008SA CE
to V
Suspend or deep powerdown modes.
Power Supply Decoupling
require careful device decoupling. System designers are
interested in 3 supply current issues: standby current
levels (I
peaks produced by falling and rising edges of CE
sient current magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will supress tran-
sient voltage peaks. Each device should have a 0.1 µF
ceramic capacitor connected between each V
GND, and between its V
quency, low inherent-inductance capacitors should be
placed as close as possible to package leads. Addition-
12
The LH28F008SA will often be used in large memory
Lowest possible memory power dissipation
Complete assurance that data bus contention will
not occur
To efficiently use these control input, an address de-
(20M array 10K file) = 2,000 file writes before erase required.
(2000 files writes/erase) × (100,000 cycles per LH28F008SA
block) = 200 million file writes. (200 × 10
minutes/write) × 1 hr/60 minutes) = 33.3 × 10
RY
RY
Flash memory power switching characteristics
»
/ BY
IH
»
»
. RY
/ BY
/ BY
SB
»
and Byte Write/Block Erase Polling
»
»
»
/ BY
can be connected to the interrupt input of the
), active current levels (I
is a full CMOS output that provides a hard-
»
is also V
»
OH
, while OE
PP
when the device is in Erase
and GND. These high fre-
»
or OE
OH
»
should be connected
WHRL
when the WSM has
6
»
CC
inputs are brought
file writes) × 10
) and transient
2
after a write or
CC
MTBF.
if unused.
CC
»
. Tran-
and
ally, for every 8 devices, a 4.7 µF electrolytic capacitor
should be placed at the array’s power supply connec-
tion between V
come voltage slumps caused by PC board trace
inductances.
V
target system, requires that the printed circuit board
designer pay attention to the V
The V
ing and erasing. Use similar trace widths and layout con-
siderations given to the V
Supply traces and decoupling will decrease V
age spikes and overshoots.
V
Command/Status Registers
anteed if V
of the Status Register (SR.3) is set to '1', a Clear Status
Register command MUST be issued before further byte
write/block erase attempts are allowed by the WSM.
Otherwise, the Byte Write (SR.4) or Erase (SR.5) Sta-
tus bits of the Status Register will be set to '1's if error is
detected. PWD transitions to VIL during byte write and
block erase also abort the operations. Data is partially
altered in either case, and the command sequence must
be repeated after normal operation is restored. Device
poweroff, or PWD transitions to V
Register to initial value 10,000 for the upper 5 bits.
issued by system software and is not altered by V
CE
up, after exit from deep powerdown or after V
tions below V
after V
Interface must be reset to Read Array mode via the Read
Array command if access to the memory array is
desired.
Power Up/Down Protection
against accidental block erasure or byte writing during
power transitions. Upon power-up, the LH28F008SA is
indifferent as to which power supply, V
ers up first. Power supply sequencing is not required.
Internal circuitry in the LH28F008SA ensures that the
Command User Interface is reset to the Read Array
mode on power up.
PP
CC
Writing flash memories, while they reside in the
Byte write and block erase completion are not guar-
The Command User Interface latches commands as
After byte write or block erase is complete, even
The LH28F008SA is designed to offer protection
»
transitions or WSM actions. Its state upon power
, V
Trace on Printed Circuit Boards
PP
PP
PP
pin supplies the memory cell current for writ-
transitions down to V
, PWD Transitions and the
PP
LKO
drops below V
CC
, is Read Array Mode.
and GND. The bulk capacitor will over-
CC
8M (1M × 8) Flash Memory
power bus. Adequate V
PPH
PPL
PP
. If the V
, the Command User
power supply trace.
IL
, clear the Status
PP
PP
or V
Status bit
CC
CC
PP
transi-
, pow-
PP
volt-
PP
or