JS28F128P30T85 Micron Technology Inc, JS28F128P30T85 Datasheet - Page 27

• Manufacturer Part Number: JS28F128P30T85
• Manufacturer: Micron Technology Inc

Specifications of JS28F128P30T85

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85/17ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

P30
7.0
7.1
Note:
7.2
August 2008
Order Number: 306666-12
RCR[15] is set (see
Asynchronous page-mode reads can only be performed when Read Configuration Register bit
Read Operation
The device supports two read modes: asynchronous page mode and synchronous burst
mode. Asynchronous page mode is the default read mode after device power-up or a
reset. The Read Configuration Register must be configured to enable synchronous burst
reads of the flash memory array (see
page
The device can be in any of four read states: Read Array, Read Identifier, Read Status
or Read CFI. Upon power-up, or after a reset, the device defaults to Read Array. To
change the read state, the appropriate read command must be written to the device
(see
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read
mode and the device is set to Read Array. However, to perform array reads after any
other device operation (e.g. write operation), the Read Array command must be issued
in order to read from the flash memory array.
To perform an asynchronous page-mode read, an address is driven onto the Address
bus, and CE# and ADV# are asserted. WE# and RST# must already have been
deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven
high to latch the address, or it must be held low throughout the read cycle. CLK is not
used for asynchronous page-mode reads, and is ignored. If only asynchronous reads
are to be performed, CLK should be tied to a valid V
and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial
access time t
In asynchronous page mode, four data words are “sensed” simultaneously from the flash
memory array and loaded into an internal page buffer. The buffer word corresponding
to the initial address on the Address bus is driven onto DQ[15:0] after the initial access
delay. The lowest two address bits determine which word of the 4-word page is output
from the data buffer at any given time.
Synchronous Burst-Mode Read
To perform a synchronous burst-read, an initial address is driven onto the Address bus,
and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.
ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can
remain asserted throughout the burst access, in which case the address is latched on
the next valid CLK edge while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the
data buffer on the next valid CLK edge after the initial access latency delay (see
11.2.2, “Latency Count” on page
following a minimum delay. However, for a synchronous non-array read, the same word
of data will be output on successive clock edges until the burst length requirements are
satisfied. Refer to the following waveforms for more detailed information:
•
•
•
Figure 24, “Synchronous Single-Word Array or Non-array Read Timing” on page 61
Figure 25, “Continuous Burst Read, Showing An Output Delay Timing” on page 62
Figure 26, “Synchronous Burst-Mode Four-Word Read Timing” on page 62
Section 6.0, “Command Set” on page
41).
Section 11.2, “Read Configuration Register” on page
AVQV
delay. (see
Section 15.0, “AC Characteristics” on page
42). Subsequent data is output on valid CLK edges
Section 11.2, “Read Configuration Register” on
24).
IH
level, WAIT signal can be floated
41).
55).
Section
Datasheet
27