JS28F128P30T85 Micron Technology Inc, JS28F128P30T85 Datasheet - Page 6

• Manufacturer Part Number: JS28F128P30T85
• Manufacturer: Micron Technology Inc

Specifications of JS28F128P30T85

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85/17ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

1.3
Table 1:
Table 2:
Datasheet
6
Lower Param Die
Upper Param Die
Lower Param Die
Upper Param Die
Virtual Chip Enable Truth Table for 512 Mb (QUAD+ Package)
Virtual Chip Enable Truth Table for 512 Mb (Easy BGA & TSOP Packages)
The P30 protection register allows unique flash device identification that can be used to
increase system security. The individual Block Lock feature provides zero-latency block
locking and unlocking. In addition, the P30 device also has four pre-defined spaces in
the main array that can be configured as One-Time Programmable (OTP).
Virtual Chip Enable Description
The P30 512Mbit devices employ a Virtual Chip Enable which combines two 256-Mbit
die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA and
TSOP packages. (Refer to
(Quad+ package) or A25 (Easy BGA and TSOP packages) is then used to select
between the die pair with F1-CE# / CE# asserted depending upon the package option
used. When chip enable is asserted and QUAD+ A24 (Easy BGA/TSOP A25) is low (
The lower parameter die is selected; when chip enable is asserted and QUAD+ A24
(Easy BGA/TSOP A25) is high (
Table 1
Die Selected
Die Selected
and
Table 2
for additional details.
Figure 9 on page 21
V
IH
), the upper parameter die is selected. Refer to
F1-CE#
CE#
and
L
L
L
L
Figure 10 on page
21). Address A24
A24
A25
H
L
H
L
August 2008
306666-12
V
IL
P30
),