JS28F128P30T85 Micron Technology Inc, JS28F128P30T85 Datasheet - Page 40

• Manufacturer Part Number: JS28F128P30T85
• Manufacturer: Micron Technology Inc

Specifications of JS28F128P30T85

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85/17ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

11.0
11.1
Table 18: Status Register Description (Sheet 1 of 2)
Datasheet
40
Status Register (SR)
Device Write
Status
DWS
Bit
7
7
6
5
4
3
Erase Suspend
Registers
When non-array reads are performed in asynchronous page mode only the first data is
valid and all subsequent data are undefined. When a non-array read operation occurs
as synchronous burst mode, the same word of data requested will be output on
successive clock edges until the burst length requirements are satisfied.
Read Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. Status Register data is automatically
made available following a Word Program, Block Erase, or Block Lock command
sequence. Reads from the device after any of these command sequences outputs the
device’s status until another valid command is written (e.g. Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on
DQ[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs
first) updates and latches the Status Register contents. However, reading the Status
Register in synchronous burst mode, CE# or ADV# must be toggled to update status
data.
The Device Write Status bit (SR[7]) provides overall status of the device. Status
register bits SR[6:1] present status and error information about the program, erase,
suspend, V
Erase Suspend Status (ESS)
Device Write Status (DWS)
Status
ESS
Program Status (PS)
V
6
Erase Status (ES)
PP
Status (VPPS)
Name
PP
, and block-locked operations.
Erase Status
ES
5
Program
Status
0 = Device is busy; program or erase cycle in progress; SR[0] valid.
PS
0 = VPP within acceptable limits during program or erase operation.
4
1 = Program fail or program sequence error when set with SR[5,7]
1 = Erase fail or program sequence error when set with SR[4,7].
1 = VPP < VPPLK during program or erase operation.
V
PP
1 = Device is ready; SR[6:1] are valid.
VPPS
Status
3
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
0 = Program successful.
0 = Erase successful.
Description
Program
Suspend
Status
PSS
2
Block-Locked
Status
BLS
1
Default Value = 0x80
August 2008
306666-12
Status
BEFP
BWS
0
P30