EPM9560RC208-20 Altera, EPM9560RC208-20 Datasheet - Page 12

• Manufacturer Part Number: EPM9560RC208-20
• Manufacturer: Altera

Specifications of EPM9560RC208-20

• Family Name: MAX 9000
• Memory Type: EEPROM
• # Macrocells: 560
• Number Of Usable Gates: 12000
• Frequency (max): 100MHz
• Propagation Delay Time: 20ns
• Number Of Logic Blocks/elements: 35
• # I/os (max): 153
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / Rohs Status: Not Compliant

MAX 9000 Programmable Logic Device Family Data Sheet
12
The MAX+PLUS II Compiler automatically allocates as many as three sets
of up to five parallel expanders to macrocells that require additional
product terms. Each set of expanders incurs a small, incremental timing
delay (t
Compiler uses the five dedicated product terms within the macrocell and
allocates two sets of parallel expanders; the first set includes five product
terms and the second set includes four product terms, increasing the total
delay by 2 t
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can
only lend parallel expanders and the highest-numbered macrocell can
only borrow them.
FastTrack Interconnect
In the MAX 9000 architecture, connections between macrocells and device
I/O pins are provided by the FastTrack Interconnect, a series of
continuous horizontal and vertical routing channels that traverse the
entire device. This device-wide routing structure provides predictable
performance even in complex designs. In contrast, the segmented routing
in FPGAs requires switch matrices to connect a variable number of
routing paths, increasing the delays between logic resources and reducing
performance.
with row and column interconnects.
PEXP
). For example, if a macrocell requires 14 product terms, the
PEXP
Figure 6
.
shows the interconnection of four adjacent LABs
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