EPM9560RC208-20 Altera, EPM9560RC208-20 Datasheet - Page 14

• Manufacturer Part Number: EPM9560RC208-20
• Manufacturer: Altera

Specifications of EPM9560RC208-20

• Family Name: MAX 9000
• Memory Type: EEPROM
• # Macrocells: 560
• Number Of Usable Gates: 12000
• Frequency (max): 100MHz
• Propagation Delay Time: 20ns
• Number Of Logic Blocks/elements: 35
• # I/os (max): 153
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / Rohs Status: Not Compliant

MAX 9000 Programmable Logic Device Family Data Sheet
Figure 7. MAX 9000 LAB Connections to Row & Column Interconnect
14
Dual-output
macrocell feeds
both FastTrack
Interconnect and
LAB local array.
96 Row Channels
LAB
Each macrocell drives
one row channel.
Macrocell 1
Macrocell 2
Each row of LABs has a dedicated row interconnect that routes signals
both into and out of the LABs in the row. The row interconnect can then
drive I/O pins or feed other LABs in the device. Each row interconnect has
a total of 96 channels.
column interconnect.
Each macrocell in the LAB can drive one of three separate column
interconnect channels. The column channels run vertically across the
entire device, and are shared by the macrocells in the same column. The
MAX+PLUS II Compiler optimizes connections to a column channel
automatically.
To LAB
Local Array
Figure 7
Additional multiplexer provides
column-to-row path if
macrocell drives row channel.
shows how a macrocell drives the row and
Each macrocell drives one
of three column channels.
48 Column
Channels
Altera Corporation