EPM9560RC208-20 Altera, EPM9560RC208-20 Datasheet - Page 6

• Manufacturer Part Number: EPM9560RC208-20
• Manufacturer: Altera

Specifications of EPM9560RC208-20

• Family Name: MAX 9000
• Memory Type: EEPROM
• # Macrocells: 560
• Number Of Usable Gates: 12000
• Frequency (max): 100MHz
• Propagation Delay Time: 20ns
• Number Of Logic Blocks/elements: 35
• # I/os (max): 153
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / Rohs Status: Not Compliant

MAX 9000 Programmable Logic Device Family Data Sheet
Figure 1. MAX 9000 Device Block Diagram
6
IOC
IOC
IOC
IOC
LAB Local Array
Logic Array
Block (LAB)
Macrocell
I/O Cell
(IOC)
Logic Array Blocks
The MAX 9000 architecture is based on linking high-performance, flexible
logic array modules called logic array blocks (LABs). LABs consist of
16-macrocell arrays that are fed by the LAB local array, as shown in
Figure 2 on page
Interconnect, a series of fast, continuous channels that run the entire
length and width of the device. The I/O pins are supported by I/O cells
(IOCs) located at the end of each row (horizontal) and column (vertical)
path of the FastTrack Interconnect.
Each LAB is fed by 33 inputs from the row interconnect and 16 feedback
signals from the macrocells within the LAB. All of these signals are
available within the LAB in their true and inverted form. In addition,
16 shared expander product terms (“expanders”) are available in their
inverted form, for a total of 114 signals that feed each product term in the
LAB. Each LAB is also fed by two low-skew global clocks and one global
clear that can be used for register control signals in all 16 macrocells.
IOC
IOC
IOC
IOC
7. Multiple LABs are linked together via the FastTrack
IOC
IOC
IOC
IOC
FastTrack
Interconnect
Altera Corporation
IOC
IOC
IOC
IOC