MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 113

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 10
Clock Generation Module (CGM)
10.1 Introduction
The clock generation module (CGM) generates the system clocks and generates and controls the timing
of the reset and power-on reset (POR) logic. The CGM is composed of:
10.2 Block Diagram
Freescale Semiconductor
•
•
•
Clock selection and generation circuitry
Slow-mode clock divider
Reset and stop generation timing and control
EXTAL
XTAL
Older device mask sets do not support the slow-mode clock divider feature.
Register $00E0 is reserved in older devices and provides no function.
Mask sets that do not have the slow-mode clock divider feature on the
MC68HC912B32 include: G96P, G86W, and H91F.
Mask sets that do not have the slow-mode clock divider feature on the
MC68HC12BE32 include: H54T and J38M.
Mask sets that do not have the slow-mode clock divider feature on the
MC68HC(9)12BC32 include: J15G.
CONSUMPTION
OSCILLATOR
REDUCED
÷
2
OSCILLATOR
OUT
E AND P CLOCK
GENERATOR
GENERATOR
T CLOCK
Figure 10-1. CGM Block Diagram
M68HC12B Family Data Sheet, Rev. 9.1
CLOCK DIVIDER
SLOW MODE
NOTE
SLOW E CLOCK
SLOW P CLOCK
P CLOCK (GBT)
E CLOCK (GBT)
WAIT
T CLOCK
P CLOCK
E CLOCK
TO BDLC AND TIM
TO BUSES, BDM,
SPI, SCI, ATD, RTI,
COP, PWM, FEE,
EE, RAM
TO CPU
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