MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 192
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MC68HC912B32VFU8
Manufacturer Part Number
MC68HC912B32VFU8
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC912B32VFU8.pdf
(334 pages)
Specifications of MC68HC912B32VFU8
Cpu Family
HC12
Device Core Size
16b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
32KB
Total Internal Ram Size
1KB
# I/os (max)
63
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC912B32VFU8
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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Serial Interface
14.2 Serial Communication Interface (SCI)
The SCI on the MCU is an NRZ format (one start, eight or nine data, and one stop bit) asynchronous
communication system with independent internal baud rate generation circuitry and an SCI transmitter
and receiver. It can be configured for eight or nine data bits (one of which may be designated as a parity
bit, odd or even). If enabled, parity is generated in hardware for transmitted and received data. Receiver
parity errors are flagged in hardware. The baud rate generator is based on a modulus counter, allowing
flexibility in choosing baud rates. There is a receiver wakeup feature, an idle line detect feature, a
loop-back mode, and various error detection features. Two port pins provide the external interface for the
transmitted data (TXD) and the received data (RXD). See
192
INTERNAL
LOGIC
TO
DATA BUS
Figure 14-2. Serial Communications Interface Block Diagram
SC0BD/SELECT
DIVIDER
MCLK
DETECT
PARITY
SC0CR1/SCI CTL 1
BAUD RATE
M68HC12B Family Data Sheet, Rev. 9.1
TX BAUD RATE
CLOCK
RX BAUD RATE
INT REQUEST LOGIC
SC0SR1/INT STATUS
SC0CR1/SCI CTL 1
DATA RECOVERY
INT REQUEST LOGIC
GENERATOR
PARITY
WAKEUP LOGIC
Figure
MSB
MSB
RxD BUFFER/SC0DRL
10-11 BIT SHIFT REG
TxD BUFFER/SC0DRL
SC0SR1/INT STATUS
10-11 BIT SHIFT REG
SC0CR2/SCI CTL 2
SC0CR2/SCI CTL 2
14-2.
SCI TRANSMITTER
TxMTR CONTROL
SCI RECEIVER
LSB
LSB
Freescale Semiconductor
PS1
RxD
TxD
PS0
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