MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 133

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

11.2.9 PWM Channel Counters 0–3
Read: Anytime
Write: Anytime
A write causes the PWM counter to reset to $00.
In special mode, if DISCR = 1, a write does not reset the PWM counter.
Each counter may be read anytime without affecting the count or the operation of the corresponding PWM
channel. Writes to a counter cause the counter to be reset to $00 and force an immediate load of both
duty and period registers with new values. To avoid a truncated PWM period, write to a counter while the
counter is disabled. In left-aligned output mode, resetting the counter and starting the waveform output is
controlled by a match between the period register and the value in the counter. In center-aligned output
mode, the counters operate as up/down counters, where a match in period changes the counter direction.
The duty register changes the state of the output during the period to determine the duty.
When a channel is enabled, the associated PWM counter starts at the count in the PWCNTx register
using the clock selected for that channel.
In special mode, when DISCP = 1 and is configured for left-aligned output, a match of period does not
reset the associated PWM counter.
Freescale Semiconductor
Address: $0048
Address: $0049
Address: $004A
Address: $004B
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
Figure 11-12. PWM Channel Counter 0 (PWCNT0)
Figure 11-13. PWM Channel Counter 1 (PWCNT1)
Figure 11-14. PWM Channel Counter 2 (PWCNT2)
Figure 11-15. PWM Channel Counter 3 (PWCNT3)
Bit 6
Bit 6
Bit 6
Bit 6
6
0
6
0
6
0
6
0
M68HC12B Family Data Sheet, Rev. 9.1
Bit 5
Bit 5
Bit 5
Bit 5
5
0
5
0
5
0
5
0
Bit 4
Bit 4
Bit 4
Bit 4
4
0
4
0
4
0
4
0
Bit 3
Bit 3
Bit 3
Bit 3
3
0
3
0
3
0
3
0
Bit 2
Bit 2
Bit 2
Bit 2
2
0
2
0
2
0
2
0
Bit 1
Bit 1
Bit 1
Bit 1
1
0
1
0
1
0
1
0
PWM Register Descriptions
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
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