MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 54

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Register Block
54
Addr.
$00FA
$00FB
$00FC
$00F1
$00F2
$00F3
$00F4
$00F5
$00F6
$00F7
$00F8
$00F9
Notes:
1. Available only on MC68HC912B32 and MC68HC912BC32 devices.
2. Available only on MC68HC912B32 and MC68HC12BE32 devices.
3. Available only on MC68HC(9)12BC32 devices.
FLASH EEPROM Control Register
EEPROM Test Register (EETST)
EEPROM Block Protect Register
FLASH EEPROM Configuration
FLASH EEPROM Lock Control
BDLC Analog Roundtrip Delay
BDLC State Vector Register
Register Name
EEPROM Control Register
BDLC Control Register 1
BDLC Control Register 2
FLASH EEPROM Test
Register (FEEMCR)
Register (FEELCK)
Register (FEETST)
BDLC Data Register
Register (BARD)
See page 100.
See page 100.
See page 100.
See page 102.
See page 231.
See page 237.
See page 233.
See page 239.
See page 240.
See page 95.
See page 95.
See page 96.
(FEECTL)
(EEPROG)
(EEPROT)
(BSVR)
(BCR1)
(BCR2)
(BDR)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
Figure 2-1. Register Map (Sheet 15 of 19)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
M68HC12B Family Data Sheet, Rev. 9.1
EEODD
ALOOP
BULKP
FSTE
IMSG
Bit 7
BD7
ATE
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1
= Unimplemented
EEVEN
DLOOP
RXPOL
GADR
CLKS
BD6
6
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
MARG
RX4XE
BD5
HVT
R1
I3
0
5
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Indeterminate after reset
BRPROT4 BRPROT3 BRPROT2 BRPROT1 BRPROT0
FEESWAI
EECPD
FENLV
BYTE
NBFS
BD4
R0
I2
R
4
1
0
0
0
0
0
0
0
0
0
0
0
0
0
= Reserved
FDISVFP
EECPRD
TEOD
SVFP
ROW
BO3
BD3
R
I1
3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
ERASE
TSIFR
VTCK
ERAS
BO2
BD2
R
I0
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Freescale Semiconductor
U = Unaffected
TMIFR1
EECPM
EELAT
STRE
BO1
BD1
LAT
IE
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
EEPGM
TMIFR0
BOOTP
MWPR
LOCK
ENPE
WCM
Bit 0
BD0
BO0
1
0
0
0
0
1
0
0
0
0
0
0
1