MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 240
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MC68HC912B32VFU8
Manufacturer Part Number
MC68HC912B32VFU8
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC912B32VFU8.pdf
(334 pages)
Specifications of MC68HC912B32VFU8
Cpu Family
HC12
Device Core Size
16b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
32KB
Total Internal Ram Size
1KB
# I/os (max)
63
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC912B32VFU8
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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Byte Data Link Communications (BDLC)
15.9.5 BDLC Analog Roundtrip Delay Register
Read: Anytime
Write: Once in normal modes or anytime in special mode
BARD programs the BDLC to compensate for various delays of external transceivers.
ATE — Analog Transceiver Enable Bit
RXPOL — Receive Pin Polarity Bit
BO3–BO0 — BARD Offset Bits
240
The ATE bit is used to select either the on-board or an off-chip analog transceiver.
This bit selects the polarity of an incoming signal on the receive pin. Some external analog transceivers
invert the receive signal from the J1850 bus before feeding it back to the digital receive pin.
These bits are used to compensate for the analog transceiver roundtrip delay.
expected transceiver delay with respect to BARD offset values.
0 = Select off-chip analog transceiver.
1 = Select on-board analog transceiver.
0 = Select inverted polarity, where external transceiver inverts the receive signal.
1 = Select normal/true polarity; true non-inverted signal from J1850 bus, for example, the external
transceiver does not invert the receive signal.
Address:
This device does not contain an on-board transceiver; ATE should be
cleared for proper operation.
Reset:
Read:
Write:
Figure 15-17. BDLC Analog Roundtrip Delay Register (BARD)
$00FC
Bit 7
ATE
1
= Unimplemented
RXPOL
M68HC12B Family Data Sheet, Rev. 9.1
6
1
5
0
0
NOTE
4
0
0
BO3
3
0
BO2
2
1
BO1
1
1
Table 15-5
Freescale Semiconductor
Bit 0
BO0
1
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