MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 222

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Byte Data Link Communications (BDLC)
15.7.3.1 Logic 0
A logic 0 is defined as:
See
15.7.3.2 Logic 1
A logic 1 is defined as:
See
15.7.3.3 Normalization Bit (NB)
The NB symbol has the same property as a logic 1 or a logic 0. It is used only in IFR message responses.
15.7.3.4 Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition followed by an active period of at least 240
µs (see
222
ACTIVE
PASSIVE
ACTIVE
PASSIVE
•
•
•
•
Figure
Figure
An active-to-passive transition followed by a passive period 64 µs in length, or
A passive-to-active transition followed by an active period 128 µs in length
An active-to-passive transition followed by a passive period 128 µs in length, or
A passive-to-active transition followed by an active period 64 µs in length
Figure
15-5(A).
15-5(B).
15-5(C)).
ACTIVE
PASSIVE
ACTIVE
PASSIVE
Figure 15-5. J1850 VPW Symbols with Nominal Symbol Times
(F) END OF FRAME
(C) BREAK
≥ 240 µs
280 µs
M68HC12B Family Data Sheet, Rev. 9.1
(G) INTER-FRAME
SEPARATION
128 µs
128 µs
20 µs
300 µs
(A) LOGIC 0
(B) LOGIC 1
(D) START OF FRAME
200 µs
OR
OR
IDLE > 300 µs
(H) IDLE
64 µs
64 µs
Freescale Semiconductor
(E) END OF DATA
200 µs