PCD3316T NXP Semiconductors, PCD3316T Datasheet - Page 12

• Manufacturer Part Number: PCD3316T
• Manufacturer: NXP Semiconductors

Specifications of PCD3316T

• Process Technology: CMOS
• Operating Frequency (max): 3580kHz
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
9397 750 04824
Product specification
7.12.5 I
The device that acknowledges must pull down the SDA line during the acknowledge
clock period immediately after the 8th SCL pulse, so that the SDA line is stable LOW
during the HIGH period of the acknowledge related clock pulse (set-up and hold
times must be taken into consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Before any data is transmitted on the I
addressed first. The addressing is always carried out with first byte transmitted after
the START procedure. One I
(1110 0000 for write and 1110 0001 for read).
The I
the write sequence and the read sequence. Both sequences are initiated with a
START condition (S) from the I
address with the read bit cleared. The first byte after the I
interpreted as the address of a PCD3316 register.During the write sequence the
register address of the PCD3316 is auto-incremented on each acknowledge. The
write sequence is ended with a STOP condition from the master. If the addressed
register is read-only or non-existent, nothing will be changed.
For the read sequence the bus master issues a repeated START condition followed
by the PCD3316 slave address with the read bit set. Then data is read from
previously set address and sent out. When the master responds with an acknowledge
the address of the register is auto incremented and the slave will put the data from
the next register on the bus. The read sequence is stopped when the master stops
giving an acknowledge and generates a STOP condition.
When a non-existing register is addressed the PCD3316 will return FFH. Existing
register addresses are shown in
reserved for test purposes. This address cannot be reached with the auto-increment
function of the I
2
idth
Fig 12. I
C-bus protocol
BY TRANSMITTER
2
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
C-bus protocol is shown in
SCL FROM
2
MASTER
C-bus acknowledge.
2
C-bus interface.
condition
START
S
11 March 1999
2
C-bus slave address is reserved for the PCD3316, E0H
2
C-bus master which is followed by the PCD3316 slave
Section
Figure
1
2
C-bus, the device which should respond is
13. Two different sequences are considered,
7.13. An additional register address (73H) is
2
not acknowledge
2
C-bus address is
© Philips Electronics N.V. 1999. All rights reserved.
acknowledge
8
PCD3316
acknowledgement
CIDCW receiver
clock pulse for
9
MBC602
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