PCD3316T NXP Semiconductors, PCD3316T Datasheet - Page 17
PCD3316T
Manufacturer Part Number
PCD3316T
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PCD3316T.pdf
(30 pages)
Specifications of PCD3316T
Process Technology
CMOS
Operating Frequency (max)
3580kHz
Mounting
Surface Mount
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PCD3316T
Manufacturer:
INFINEON
Quantity:
6 897
Company:
Part Number:
PCD3316T/2
Manufacturer:
NXPL
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Part Number:
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Philips Semiconductors
Table 13: Mode register 1
Address: 04H; read/write.
Table 14: Description of CIDMD1 bits
Table 15: Mode register 2
Address: 05H; read/write.
Table 16: Description of CIDMD2 bits
9397 750 04824
Product specification
Bit
CIDMD1.7
CIDMD1.6
CIDMD1.5
CIDMD1.4
CIDMD1.3
CIDMD1.2 to
CIDMD1.0
Bit
CIDMD2.7
CIDMD2.6
CIDMD2.5
CIDMD2.4
CIDMD2.3 to
CIDMD2.0
FSK on/off
XTAL on/off
7
7
Symbol
FSK on/off
FSK-BOM-mask on/off
CAS on/off
POL on/off
INT polarity HIGH/LOW INT polarity HIGH/LOW = 0: interrupt pin active LOW;
Symbol
XTAL on/off
TB on/off
SEC/MIN
INT-SUP on/off
FSK-BOM-mask on/off
7.13.5 Mode register 1 (CIDMD1)
7.13.6 Mode register 2 (CIDMD2)
TB on/off
6
6
Description
FSK on/off = 0: FSK receiver disabled; FSK on/off = 1: FSK receiver enabled
FSK-BOM-mask on/off = 0: FSK interrupts will be generated when a data word was
received even before mark period (data from channel seizure);
FSK-BOM-mask on/off = 1: FSK interrupts will only be generated after the mark
period was detected (no interrupts from channel seizure)
CAS on/off = 0: CAS detector disabled; CAS on/off = 1: CAS detector enabled
POL on/off = 0: disable interrupts due to polarity change;
POL on/off = 1: enable interrupts due to polarity change
INT polarity HIGH/LOW = 1: interrupt pin active HIGH
reserved bits
Description
XTAL on/off = 0: disable 3.58 MHz oscillator;
XTAL on/off = 1: enable 3.58 MHz oscillator
TB on/off = 0: disable 32.768 kHz timebase;
TB on/off = 1: enable 32.768 kHz timebase
SEC/MIN = 0: every minute a timebase interrupt;
SEC/MIN = 1: every second a timebase interrupt
INT-SUP on/off = 0: enable SEC/MIN interrupts during FSK reception;
INT-SUP on/off = 1: disable SEC/MIN interrupts during FSK reception
reserved bits
CAS on/off
SEC/MIN
5
5
11 March 1999
POL on/off
INT-SUP on/off
4
4
INT polarity HIGH/LOW
3
3
2
© Philips Electronics N.V. 1999. All rights reserved.
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CIDCW receiver
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