PCD3316T NXP Semiconductors, PCD3316T Datasheet - Page 20

• Manufacturer Part Number: PCD3316T
• Manufacturer: NXP Semiconductors

Specifications of PCD3316T

• Process Technology: CMOS
• Operating Frequency (max): 3580kHz
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
Table 18: Characteristics
V
specified.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Pins SCL and SDA are equipped with an open-drain output buffer. The pins have no clamp diode to V
[11] The input threshold voltage of SCL and SDA meet the I
[12] Maximum capacitive load for each bus line is 400 pF.
[13] C1
9397 750 04824
Product specification
Symbol
3.58 MHz oscillator (pins HXIN and HXOUT)
V
Z
C1
32 kHz oscillator (pins LXIN and LXOUT)
g
C
C
DD
m
HXIN(p-p)
i(HXIN)
i(LXIN)
o(LXOUT)
i
; C2
= 2.5 to 3.6 V; T
Except for FSK and CAS detection, all circuitry works already when V
acknowledge), the application can start reading the LOW-BAT Indication bit (Status register, bit 5) to check whether the supply voltage
has reached the operating voltage level. A voltage divider network can be connected to pins V
V
The power-on reset LOW level is defined as V
32 kHz oscillator on (MIN Interrupt, SEC Interrupt, Polarity change, Low battery and Level detect available).
3.58 MHz oscillator on (device fully operational).
GND < V
an Electrostatic Stress on the pin.
When FSK is selected the signal power is measured between 1000 and 2200 Hz. When CAS is selected signal levels are measured
between 2000 and 2800 Hz.
The IRQ pin is implemented as a 3-state pin which is only active (either HIGH or LOW) when an interrupt occurs. A pull-up or pull-down
has to be connected to define the line when no interrupt is generated.
Verified on sampling basis.
According to Bellcore specification: near end speech level
to method B of recommendation P.56.
as a logic 0 and an input voltage above 0.7V
LOWBAT
i
i
and C2
= V
I
Parameter
external clock signal amplitude
(peak-to-peak value) on pin HXIN
input impedance on pin HXIN
input capacitance on pins HXIN and
HXOUT
transconductance
LXIN input capacitance
LXOUT output capacitance
< V
i
are the total internal capacitances (including gate capacitance and leadframe capacitance).
ref
DD
if V
. The leakage currents are generally very small, <1 nA. The value given here, 1 A, is a maximum that can occur after
amb
DD
[13]
= V
= 25 to +70 C; HXIN = 3.579545 MHz 0.05%; LXIN = 32.768 kHz 0.1%; unless otherwise
DD(min)
…continued
.
DD
POR(L)
will be recognized as a logic 1
= V
2
C-bus specification. Therefore, an input voltage below 0.3V
POR(H)
11 March 1999
Conditions
V
i(p-p)
7 dBm ASL (ASL = Active Speech Level), referenced to 600 , according
< 50 mV
V
hys(POR)
DD
> V
. By design V
POR(H)
. Since the I
POR(L)
is always lower than V
DD
2
C-bus interface will work (starts to
, LOWBAT and AGND/DGND such that
Min
0.5
300
2
DD
© Philips Electronics N.V. 1999. All rights reserved.
.
Typ
1000
10
4
13
10
PCD3316
CIDCW receiver
DD
POR(H)
Max
V
10
will be recognized
DD
.
Unit
V
k
pF
pF
pF
20 of 30
S